Merge commit 'u-boot-fdt/testing'

[oweals/u-boot.git] / include / asm-ppc / processor.h

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 71e2e847a46454015a990d4997b0e2d8f4428fb2..f58b38aace65de1b11941643cd11cdb05e52f07c 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -91,6 +91,11 @@
 
 /* Special Purpose Registers (SPRNs)*/
 
+/* PPC440 Architecture is BOOK-E */
+#ifdef CONFIG_440
+#define CONFIG_BOOKE
+#endif
+
 #define SPRN_CDBCR     0x3D7   /* Cache Debug Control Register */
 #define SPRN_CTR       0x009   /* Count Register */
 #define SPRN_DABR      0x3F5   /* Data Address Breakpoint Register */
@@ -217,12 +222,14 @@
 #define   HID0_DPM     (1<<20)
 #define   HID0_ICE     (1<<HID0_ICE_SHIFT)     /* Instruction Cache Enable */
 #define   HID0_DCE     (1<<HID0_DCE_SHIFT)     /* Data Cache Enable */
+#define   HID0_TBEN    (1<<14)         /* Time Base Enable */
 #define   HID0_ILOCK   (1<<13)         /* Instruction Cache Lock */
 #define   HID0_DLOCK   (1<<HID0_DLOCK_SHIFT)   /* Data Cache Lock */
 #define   HID0_ICFI    (1<<11)         /* Instr. Cache Flash Invalidate */
 #define   HID0_DCFI    (1<<10)         /* Data Cache Flash Invalidate */
 #define   HID0_DCI     HID0_DCFI
 #define   HID0_SPD     (1<<9)          /* Speculative disable */
+#define   HID0_ENMAS7  (1<<7)          /* Enable MAS7 Update for 36-bit phys */
 #define   HID0_SGE     (1<<7)          /* Store Gathering Enable */
 #define   HID0_SIED    HID_SGE         /* Serial Instr. Execution [Disable] */
 #define   HID0_DCFA    (1<<6)          /* Data Cache Flush Assist */
@@ -450,6 +457,7 @@
 #define SPRN_PID1       0x279   /* Process ID Register 1 */
 #define SPRN_PID2       0x27a   /* Process ID Register 2 */
 #define SPRN_MCSR      0x23c   /* Machine Check Syndrome register */
+#define SPRN_MCAR      0x23d   /* Machine Check Address register */
 #ifdef CONFIG_440
 #define MCSR_MCS       0x80000000      /* Machine Check Summary */
 #define MCSR_IB                0x40000000      /* Instruction PLB Error */
@@ -464,7 +472,8 @@
 #define ESR_ST          0x00800000      /* Store Operation */
 
 #if defined(CONFIG_MPC86xx)
-#define SPRN_MSSCRO    0x3f6
+#define SPRN_MSSCR0    0x3f6
+#define SPRN_MSSSR0    0x3f7
 #endif
 
 
@@ -531,7 +540,7 @@
 #define LR     SPRN_LR
 #define MBAR    SPRN_MBAR       /* System memory base address */
 #if defined(CONFIG_MPC86xx)
-#define MSSCR0 SPRN_MSSCRO
+#define MSSCR0 SPRN_MSSCR0
 #endif
 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define PIR    SPRN_PIR
@@ -761,6 +770,10 @@
 #define PVR_405EP_RA   0x51210950
 #define PVR_405GPR_RB  0x50910951
 #define PVR_405EZ_RA   0x41511460
+#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */
+#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */
+#define PVR_405EX1_RA  0x12911477 /* 405EX rev A with Security */
+#define PVR_405EX2_RA  0x12911475 /* 405EX rev A without Security */
 #define PVR_440GP_RB   0x40120440
 #define PVR_440GP_RC   0x40120481
 #define PVR_440EP_RA   0x42221850