ap325rxa/favr-32-ezkit: Use CONFIG_FLASH_CFI_DRIVER

[oweals/u-boot.git] / include / asm-ppc / processor.h

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 673485777ef26cfe6f7cf7fa5cfbab72f07e7618..e07e5d3be8f191c69548c5705a30d0e75e11ec96 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -426,6 +426,7 @@
 /* e500 definitions */
 #define SPRN_L1CFG0    0x203   /* L1 Cache Configuration Register 0 */
 #define SPRN_L1CFG1    0x204   /* L1 Cache Configuration Register 1 */
+#define SPRN_L2CFG0    0x207   /* L2 Cache Configuration Register 0 */
 #define SPRN_L1CSR0    0x3f2   /* L1 Data Cache Control and Status Register 0 */
 #define   L1CSR0_CPE           0x00010000      /* Data Cache Parity Enable */
 #define   L1CSR0_DCFI          0x00000002      /* Data Cache Flash Invalidate */
@@ -434,6 +435,21 @@
 #define   L1CSR1_CPE           0x00010000      /* Instruction Cache Parity Enable */
 #define   L1CSR1_ICFI          0x00000002      /* Instruction Cache Flash Invalidate */
 #define   L1CSR1_ICE           0x00000001      /* Instruction Cache Enable */
+#define SPRN_L1CSR2    0x25e   /* L1 Data Cache Control and Status Register 2 */
+#define SPRN_L2CSR0    0x3f9   /* L2 Data Cache Control and Status Register 0 */
+#define   L2CSR0_L2E           0x80000000      /* L2 Cache Enable */
+#define   L2CSR0_L2PE          0x40000000      /* L2 Cache Parity/ECC Enable */
+#define   L2CSR0_L2WP          0x1c000000      /* L2 I/D Way Partioning */
+#define   L2CSR0_L2CM          0x03000000      /* L2 Cache Coherency Mode */
+#define   L2CSR0_L2FI          0x00200000      /* L2 Cache Flash Invalidate */
+#define   L2CSR0_L2IO          0x00100000      /* L2 Cache Instruction Only */
+#define   L2CSR0_L2DO          0x00010000      /* L2 Cache Data Only */
+#define   L2CSR0_L2REP         0x00003000      /* L2 Line Replacement Algo */
+#define   L2CSR0_L2FL          0x00000800      /* L2 Cache Flush */
+#define   L2CSR0_L2LFC         0x00000400      /* L2 Cache Lock Flash Clear */
+#define   L2CSR0_L2LOA         0x00000080      /* L2 Cache Lock Overflow Allocate */
+#define   L2CSR0_L2LO          0x00000020      /* L2 Cache Lock Overflow */
+#define SPRN_L2CSR1    0x3fa   /* L2 Data Cache Control and Status Register 1 */
 
 #define SPRN_MMUCSR0   0x3f4   /* MMU control and status register 0 */
 #define SPRN_MAS0      0x270   /* MMU Assist Register 0 */
@@ -624,8 +640,12 @@
 #define MCSRR1 SPRN_MCSRR1
 #define L1CSR0 SPRN_L1CSR0
 #define L1CSR1 SPRN_L1CSR1
+#define L1CSR2 SPRN_L1CSR2
 #define L1CFG0 SPRN_L1CFG0
 #define L1CFG1 SPRN_L1CFG1
+#define L2CFG0 SPRN_L2CFG0
+#define L2CSR0 SPRN_L2CSR0
+#define L2CSR1 SPRN_L2CSR1
 #define MCSR   SPRN_MCSR
 #define MMUCSR0        SPRN_MMUCSR0
 #define BUCSR  SPRN_BUCSR
@@ -810,6 +830,10 @@
 #define PVR_460EX_RA   0x130218A3 /* 460EX rev A without Security Engine */
 #define PVR_460GT_SE_RA        0x130218A0 /* 460GT rev A with Security Engine    */
 #define PVR_460GT_RA   0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_460SX_RA    0x13541800 /* 460SX rev A                   */
+#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
+#define PVR_460GX_RA    0x13541802 /* 460GX rev A                   */
+#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
 #define PVR_601                0x00010000
 #define PVR_602                0x00050000
 #define PVR_603                0x00030000
@@ -835,6 +859,8 @@
 #define PVR_86xx       0x80040000
 #define PVR_86xx_REV1  (PVR_86xx | 0x0010)
 
+#define PVR_VIRTEX5     0x7ff21912
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
@@ -900,6 +926,8 @@
 
 #define SVR_8533       0x803400
 #define SVR_8533_E     0x803C00
+#define SVR_8536       0x803700
+#define SVR_8536_E     0x803F00
 #define SVR_8540       0x803000
 #define SVR_8541       0x807200
 #define SVR_8541_E     0x807A00