ppc4xx: PPC44x MQ initialization

[oweals/u-boot.git] / include / asm-ppc / ppc4xx-sdram.h

diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index 2ba5619d7df90c25db59dac05e898cc8188989eb..98faced366c814b387a9e0baad43e35f5b9ece1e 100644 (file)
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -272,8 +272,11 @@
 #define SDRAM_CONF1HB_PRPD     0x00080000      /* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1HB_PWPD     0x00040000      /* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1HB_PRW      0x00020000      /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPLM     0x00001000      /* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1HB_RPEN     0x00000800      /* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1HB_RFTE     0x00000400      /* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1HB_WRCL     0x00000080      /* MCIF Cycle Limit 1 - Bits 22..24 */
+#define SDRAM_CONF1HB_MASK     0x0000F380      /* RPLM & WRCL mask */
 
 #define SDRAM_ERRSTATHB                (SDRAMQ_DCR_BASE+0x7)   /* error status HB             */
 #define SDRAM_ERRADDUHB                (SDRAMQ_DCR_BASE+0x8)   /* error address upper 32 HB   */
@@ -284,8 +287,10 @@
 #define SDRAM_CONF1LL_PRPD     0x00080000              /* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1LL_PWPD     0x00040000              /* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1LL_PRW      0x00020000              /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1LL_RPLM     0x00001000              /* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1LL_RPEN     0x00000800              /* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1LL_RFTE     0x00000400              /* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1LL_MASK     0x0000F000              /* RPLM mask */
 
 #define SDRAM_ERRSTATLL                (SDRAMQ_DCR_BASE+0xC)   /* error status LL             */
 #define SDRAM_ERRADDULL                (SDRAMQ_DCR_BASE+0xD)   /* error address upper 32 LL   */
@@ -1403,12 +1408,6 @@
 #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
 
 #ifndef __ASSEMBLY__
-
-struct sdram_timing {
-       u32 wrdtr;
-       u32 clktr;
-};
-
 /*
  * Prototypes
  */