85xx: properly document MPC85xx_PORDEVSR2_SEC_CFG

[oweals/u-boot.git] / include / asm-ppc / ppc4xx-sdram.h

diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index df787b3d4c7d961a2031263916956a3135f9a1da..98faced366c814b387a9e0baad43e35f5b9ece1e 100644 (file)
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -29,6 +29,7 @@
 /*
  * SDRAM Controller
  */
+
 /*
  * XXX - ToDo: Revisit file to change all these lower case defines into
  * upper case. Also needs to be done in the controller setup code too
@@ -256,28 +257,49 @@
 #define SDRAM_DLYCAL_DLCV_ENCODE(x)    (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 #define SDRAM_DLYCAL_DLCV_DECODE(x)    (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 
+#if !defined(CONFIG_405EX)
 /*
  * Memory queue defines
  */
-#define SDRAMQ_DCR_BASE        0x040
-
-#define SDRAM_R0BAS    (SDRAMQ_DCR_BASE+0x0)   /* rank 0 base address & size  */
-#define SDRAM_R1BAS    (SDRAMQ_DCR_BASE+0x1)   /* rank 1 base address & size  */
-#define SDRAM_R2BAS    (SDRAMQ_DCR_BASE+0x2)   /* rank 2 base address & size  */
-#define SDRAM_R3BAS    (SDRAMQ_DCR_BASE+0x3)   /* rank 3 base address & size  */
-#define SDRAM_CONF1HB  (SDRAMQ_DCR_BASE+0x5)   /* configuration 1 HB          */
-#define SDRAM_ERRSTATHB        (SDRAMQ_DCR_BASE+0x7)   /* error status HB             */
-#define SDRAM_ERRADDUHB        (SDRAMQ_DCR_BASE+0x8)   /* error address upper 32 HB   */
-#define SDRAM_ERRADDLHB        (SDRAMQ_DCR_BASE+0x9)   /* error address lower 32 HB   */
-#define SDRAM_PLBADDULL        (SDRAMQ_DCR_BASE+0xA)   /* PLB base address upper 32 LL */
-#define SDRAM_CONF1LL  (SDRAMQ_DCR_BASE+0xB)   /* configuration 1 LL          */
-#define SDRAM_ERRSTATLL        (SDRAMQ_DCR_BASE+0xC)   /* error status LL             */
-#define SDRAM_ERRADDULL        (SDRAMQ_DCR_BASE+0xD)   /* error address upper 32 LL   */
-#define SDRAM_ERRADDLLL        (SDRAMQ_DCR_BASE+0xE)   /* error address lower 32 LL   */
-#define SDRAM_CONFPATHB        (SDRAMQ_DCR_BASE+0xF)   /* configuration between paths */
-#define SDRAM_PLBADDUHB        (SDRAMQ_DCR_BASE+0x10)  /* PLB base address upper 32 LL */
+#define SDRAMQ_DCR_BASE 0x040
+
+#define SDRAM_R0BAS            (SDRAMQ_DCR_BASE+0x0)   /* rank 0 base address & size  */
+#define SDRAM_R1BAS            (SDRAMQ_DCR_BASE+0x1)   /* rank 1 base address & size  */
+#define SDRAM_R2BAS            (SDRAMQ_DCR_BASE+0x2)   /* rank 2 base address & size  */
+#define SDRAM_R3BAS            (SDRAMQ_DCR_BASE+0x3)   /* rank 3 base address & size  */
+#define SDRAM_CONF1HB          (SDRAMQ_DCR_BASE+0x5)   /* configuration 1 HB          */
+#define SDRAM_CONF1HB_AAFR     0x80000000      /* Address Ack on First Request - Bit 0 */
+#define SDRAM_CONF1HB_PRPD     0x00080000      /* PLB Read pipeline Disable - Bit 12 */
+#define SDRAM_CONF1HB_PWPD     0x00040000      /* PLB Write pipeline Disable - Bit 13 */
+#define SDRAM_CONF1HB_PRW      0x00020000      /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPLM     0x00001000      /* Read Passing Limit 1 - Bits 16..19 */
+#define SDRAM_CONF1HB_RPEN     0x00000800      /* Read Passing Enable - Bit 20 */
+#define SDRAM_CONF1HB_RFTE     0x00000400      /* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1HB_WRCL     0x00000080      /* MCIF Cycle Limit 1 - Bits 22..24 */
+#define SDRAM_CONF1HB_MASK     0x0000F380      /* RPLM & WRCL mask */
+
+#define SDRAM_ERRSTATHB                (SDRAMQ_DCR_BASE+0x7)   /* error status HB             */
+#define SDRAM_ERRADDUHB                (SDRAMQ_DCR_BASE+0x8)   /* error address upper 32 HB   */
+#define SDRAM_ERRADDLHB                (SDRAMQ_DCR_BASE+0x9)   /* error address lower 32 HB   */
+#define SDRAM_PLBADDULL                (SDRAMQ_DCR_BASE+0xA)   /* PLB base address upper 32 LL */
+#define SDRAM_CONF1LL          (SDRAMQ_DCR_BASE+0xB)   /* configuration 1 LL          */
+#define SDRAM_CONF1LL_AAFR     0x80000000              /* Address Ack on First Request - Bit 0 */
+#define SDRAM_CONF1LL_PRPD     0x00080000              /* PLB Read pipeline Disable - Bit 12 */
+#define SDRAM_CONF1LL_PWPD     0x00040000              /* PLB Write pipeline Disable - Bit 13 */
+#define SDRAM_CONF1LL_PRW      0x00020000              /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1LL_RPLM     0x00001000              /* Read Passing Limit 1 - Bits 16..19 */
+#define SDRAM_CONF1LL_RPEN     0x00000800              /* Read Passing Enable - Bit 20 */
+#define SDRAM_CONF1LL_RFTE     0x00000400              /* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1LL_MASK     0x0000F000              /* RPLM mask */
+
+#define SDRAM_ERRSTATLL                (SDRAMQ_DCR_BASE+0xC)   /* error status LL             */
+#define SDRAM_ERRADDULL                (SDRAMQ_DCR_BASE+0xD)   /* error address upper 32 LL   */
+#define SDRAM_ERRADDLLL                (SDRAMQ_DCR_BASE+0xE)   /* error address lower 32 LL   */
+#define SDRAM_CONFPATHB                (SDRAMQ_DCR_BASE+0xF)   /* configuration between paths */
+#define SDRAM_CONFPATHB_TPEN   0x08000000              /* Transaction Passing Enable - Bit 4 */
+
+#define SDRAM_PLBADDUHB                (SDRAMQ_DCR_BASE+0x10)  /* PLB base address upper 32 LL */
 
-#if !defined(CONFIG_405EX)
 /*
  * Memory Bank 0-7 configuration
  */
@@ -1385,4 +1407,18 @@
 
 #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
 
+#ifndef __ASSEMBLY__
+/*
+ * Prototypes
+ */
+void inline blank_string(int size);
+inline void ppc4xx_ibm_ddr2_register_dump(void);
+u32 mfdcr_any(u32);
+void mtdcr_any(u32, u32);
+u32 ddr_wrdtr(u32);
+u32 ddr_clktr(u32);
+void spd_ddr_init_hang(void);
+u32 DQS_autocalibration(void);
+#endif /* __ASSEMBLY__ */
+
 #endif /* _PPC4xx_SDRAM_H_ */