FSL DDR: Add e500 TLB helper for DDR code

[oweals/u-boot.git] / include / asm-ppc / mmu.h

diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index ec1ca53cc165dd4379b8587554d9ba1e4e7a63e1..8975e6c90a8586e708f2770be77fa48bcf15a525 100644 (file)
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -140,11 +140,16 @@ extern void _tlbia(void);         /* invalidate all TLB entries */
 
 typedef enum {
        IBAT0 = 0, IBAT1, IBAT2, IBAT3,
-       DBAT0, DBAT1, DBAT2, DBAT3
+       DBAT0, DBAT1, DBAT2, DBAT3,
+#ifdef CONFIG_HIGH_BATS
+       IBAT4, IBAT5, IBAT6, IBAT7,
+       DBAT4, DBAT5, DBAT6, DBAT7
+#endif
 } ppc_bat_t;
 
 extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
 extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
+extern void print_bats(void);
 
 #endif /* __ASSEMBLY__ */
 
@@ -343,7 +348,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define MAS0_ESEL(x)   ((x << 16) & 0x0FFF0000)
 #define MAS0_NV(x)     ((x) & 0x00000FFF)
 
-#define MAS1_VALID     0x80000000
+#define MAS1_VALID     0x80000000
 #define MAS1_IPROT     0x40000000
 #define MAS1_TID(x)    ((x << 16) & 0x3FFF0000)
 #define MAS1_TS                0x00001000
@@ -426,8 +431,8 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
 extern void disable_tlb(u8 esel);
 extern void invalidate_tlb(u8 tlb);
 extern void init_tlbs(void);
+extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
 
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
        { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
          .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
@@ -550,14 +555,14 @@ extern int num_tlb_entries;
 /*----------------------------------------------------------------------------+
 | TLB specific defines.
 +----------------------------------------------------------------------------*/
-#define TLB_256MB_ALIGN_MASK 0xF0000000
-#define TLB_16MB_ALIGN_MASK  0xFF000000
-#define TLB_1MB_ALIGN_MASK   0xFFF00000
-#define TLB_256KB_ALIGN_MASK 0xFFFC0000
-#define TLB_64KB_ALIGN_MASK  0xFFFF0000
-#define TLB_16KB_ALIGN_MASK  0xFFFFC000
-#define TLB_4KB_ALIGN_MASK   0xFFFFF000
-#define TLB_1KB_ALIGN_MASK   0xFFFFFC00
+#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
+#define TLB_16MB_ALIGN_MASK  0xFFF000000ULL
+#define TLB_1MB_ALIGN_MASK   0xFFFF00000ULL
+#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
+#define TLB_64KB_ALIGN_MASK  0xFFFFF0000ULL
+#define TLB_16KB_ALIGN_MASK  0xFFFFFC000ULL
+#define TLB_4KB_ALIGN_MASK   0xFFFFFF000ULL
+#define TLB_1KB_ALIGN_MASK   0xFFFFFFC00ULL
 #define TLB_256MB_SIZE       0x10000000
 #define TLB_16MB_SIZE        0x01000000
 #define TLB_1MB_SIZE         0x00100000
@@ -686,7 +691,7 @@ extern int num_tlb_entries;
 #define MSYNC                          .long 0x7c000000|\
                                        (598<<1)
 
-#define MBAR_INST                              .long 0x7c000000|\
+#define MBAR_INST                              .long 0x7c000000|\
                                        (854<<1)
 
 #ifndef __ASSEMBLY__
@@ -698,7 +703,7 @@ unsigned long mftlb1(unsigned long index);
 unsigned long mftlb2(unsigned long index);
 unsigned long mftlb3(unsigned long index);
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 void remove_tlb(u32 vaddr, u32 size);
 void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
 #endif /* __ASSEMBLY__ */