Merge branch 'master' of /home/stefan/git/u-boot/u-boot

[oweals/u-boot.git] / include / asm-ppc / immap_86xx.h

diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 7526061d5ab7c11240561785701b489523198142..c03b4b81578ae406ee0f04656e20dfed993b68f6 100644 (file)
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -109,7 +109,7 @@ typedef struct ccsr_ddr {
        uint    cs4_config;             /* 0x2090 - DDR Chip Select Configuration */
        uint    cs5_config;             /* 0x2094 - DDR Chip Select Configuration */
        char    res7[104];
-       uint    ext_refrec;             /* 0x2100 - DDR SDRAM extended refresh recovery */
+       uint    timing_cfg_3;           /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
        uint    timing_cfg_0;           /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
        uint    timing_cfg_1;           /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
        uint    timing_cfg_2;           /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
@@ -119,14 +119,14 @@ typedef struct ccsr_ddr {
        uint    sdram_mode_2;           /* 0x211c - DDR SDRAM Mode Configuration 2 */
        uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
        uint    sdram_interval;         /* 0x2124 - DDR SDRAM Interval Configuration */
-       uint    sdram_data_init;        /* 0x2128 - DDR SDRAM Data Initialization */
+       uint    sdram_data_init;        /* 0x2128 - DDR SDRAM Data Initialization */
        char    res8[4];
        uint    sdram_clk_cntl;         /* 0x2130 - DDR SDRAM Clock Control */
        char    res9[12];
        uint    sdram_ocd_cntl;         /* 0x2140 - DDR SDRAM OCD Control */
        uint    sdram_ocd_status;       /* 0x2144 - DDR SDRAM OCD Status */
        uint    init_addr;              /* 0x2148 - DDR training initialzation address */
-       uint    init_addr_ext;          /* 0x214C - DDR training initialzation extended address */
+       uint    init_ext_addr;          /* 0x214C - DDR training initialzation extended address */
        char    res10[2728];
        uint    ip_rev1;                /* 0x2BF8 - DDR IP Block Revision 1 */
        uint    ip_rev2;                /* 0x2BFC - DDR IP Block Revision 2 */
@@ -464,7 +464,7 @@ typedef struct ccsr_dma {
 
 /* tsec1-4: 24000-28000 */
 typedef struct ccsr_tsec {
-       uint    id;             /* 0x24000 - Controller ID Register */
+       uint    id;             /* 0x24000 - Controller ID Register */
        char    res1[12];
        uint    ievent;         /* 0x24010 - Interrupt Event Register */
        uint    imask;          /* 0x24014 - Interrupt Mask Register */
@@ -538,7 +538,7 @@ typedef struct ccsr_tsec {
        uint    rbifx;          /* 0x24330 - Receive bit field extract control Register */
        uint    rqfar;          /* 0x24334 - Receive queue filing table address Register */
        uint    rqfcr;          /* 0x24338 - Receive queue filing table control Register */
-       uint    rqfpr;          /* 0x2433c - Receive queue filing table property Register */
+       uint    rqfpr;          /* 0x2433c - Receive queue filing table property Register */
        uint    mrblr;          /* 0x24340 - Maximum Receive Buffer Length Register */
        char    res28[56];
        uint    rbdbph;         /* 0x2437C - Receive Data Buffer Pointer High */