85xx: Added MPC8535/E identifiers

[oweals/u-boot.git] / include / asm-ppc / immap_86xx.h

diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index c03b4b81578ae406ee0f04656e20dfed993b68f6..470385ffd2f486a565f43aee00e1c84a6fb9ec75 100644 (file)
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1289,24 +1289,49 @@ typedef struct ccsr_gur {
        uint    powmgtcsr;      /* 0xe0080 - Power management status and control register */
        char    res8[12];
        uint    mcpsumr;        /* 0xe0090 - Machine check summary register */
-       char    res9[12];
+       uint    rstrscr;        /* 0xe0094 - Reset request status and control register */
+       char    res9[8];
        uint    pvr;            /* 0xe00a0 - Processor version register */
        uint    svr;            /* 0xe00a4 - System version register */
-       char    res10a[1880];
+       char    res10a[8];
+       uint    rstcr;          /* 0xe00b0 - Reset control register */
+#define MPC86xx_RSTCR_HRST_REQ 0x00000002
+       char    res10b[1868];
        uint    clkdvdr;        /* 0xe0800 - Clock Divide register */
-       char    res10b[1532];
+       char    res10c[796];
+       uint    ddr1clkdr;      /* 0xe0b20 - DDRC1 Clock Disable register */
+       char    res10d[4];
+       uint    ddr2clkdr;      /* 0xe0b28 - DDRC2 Clock Disable register */
+       char    res10e[724];
        uint    clkocr;         /* 0xe0e00 - Clock out select register */
        char    res11[12];
        uint    ddrdllcr;       /* 0xe0e10 - DDR DLL control register */
        char    res12[12];
        uint    lbcdllcr;       /* 0xe0e20 - LBC DLL control register */
-       int     res13[57];
-       uint    lynxdcr1;        /* 0xe0f08 - Lynx debug control register 1*/
-       int     res14[6];
-       uint    ddrioovcr;      /* 0xe0f24 - DDR IO Overdrive Control register */
-       char    res15[61656];
+       char    res13a[224];
+       uint    srds1cr0;       /* 0xe0f04 - SerDes1 control register 0 */
+       char    res13b[4];
+       uint    srds1cr1;       /* 0xe0f08 - SerDes1 control register 1 */
+       char    res14[24];
+       uint    ddrioovcr;      /* 0xe0f24 - DDR IO Overdrive Control register */
+       char    res15a[24];
+       uint    srds2cr0;       /* 0xe0f40 - SerDes2 control register 0 */
+       uint    srds2cr1;       /* 0xe0f44 - SerDes2 control register 1 */
+       char    res16[184];
 } ccsr_gur_t;
 
+/*
+ * Watchdog register block(0xe_4000-0xe_4fff)
+ */
+typedef struct ccsr_wdt {
+       uint    res0;
+       uint    swcrr; /* System watchdog control register */
+       uint    swcnr; /* System watchdog count register */
+       char    res1[2];
+       ushort  swsrr; /* System watchdog service register */
+       char    res2[4080];
+} ccsr_wdt_t;
+
 typedef struct immap {
        ccsr_local_mcm_t        im_local_mcm;
        ccsr_ddr_t              im_ddr1;
@@ -1330,13 +1355,15 @@ typedef struct immap {
        char                    res5[389120];
        ccsr_rio_t              im_rio;
        ccsr_gur_t              im_gur;
+       char                    res6[12288];
+       ccsr_wdt_t              im_wdt;
 } immap_t;
 
 extern immap_t  *immr;
 
-#define CFG_MPC86xx_DDR_OFFSET (0x2000)
-#define CFG_MPC86xx_DDR_ADDR   (CFG_IMMR + CFG_MPC86xx_DDR_OFFSET)
-#define CFG_MPC86xx_DDR2_OFFSET        (0x6000)
-#define CFG_MPC86xx_DDR2_ADDR  (CFG_IMMR + CFG_MPC86xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC86xx_DDR_OFFSET  (0x2000)
+#define CONFIG_SYS_MPC86xx_DDR_ADDR    (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
+#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000)
+#define CONFIG_SYS_MPC86xx_DDR2_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
 
 #endif /*__IMMAP_86xx__*/