/*
* MPC85xx Internal Memory Map
*
- * Copyright 2007 Freescale Semiconductor.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
#define __IMMAP_85xx__
#include <asm/types.h>
+#include <asm/fsl_dma.h>
#include <asm/fsl_i2c.h>
+#include <asm/fsl_lbc.h>
+
+typedef struct ccsr_local {
+ u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */
+ u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */
+ u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */
+#define CCSRAR_C 0x80000000 /* Commit */
+ u8 res1[4];
+ u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */
+ u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */
+ u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */
+ u8 res2[4];
+ u32 bstrh; /* 0x20 - Boot space translation register high */
+ u32 bstrl; /* 0x24 - Boot space translation register Low */
+ u32 bstrar; /* 0x28 - Boot space translation attributes register */
+ u8 res3[0xbd4];
+ struct {
+ u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */
+ u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */
+ u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */
+ u8 res4[4];
+ } law[32];
+ u8 res35[0x204];
+} ccsr_local_t;
/*
* Local-Access Registers and ECM Registers(0x0000-0x2000)
uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
char res19[4];
uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
- char res20[780];
+ char res19_8a[20];
+ uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
+ char res19_8b[4];
+ uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
+ char res19_9a[20];
+ uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
+ char res19_9b[4];
+ uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
+ char res19_10a[20];
+ uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */
+ char res19_10b[4];
+ uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */
+ char res19_11a[20];
+ uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */
+ char res19_11b[4];
+ uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */
+ char res20[652];
uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
char res21[12];
uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
- char res5[112];
- uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+ char res4a[48];
+ uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */
+ uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */
+ uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
+ uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
+ char res5[48];
+ uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
char res6[4];
uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
char res7[20];
- uint init_address; /* 0x2148 - DDR training initialization address */
- uint init_ext_address; /* 0x214C - DDR training initialization extended address */
- char res8_1[2728];
+ uint init_addr; /* 0x2148 - DDR training initialization address */
+ uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
+ char res8_1[16];
+ uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
+ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
+ char reg8_1a[8];
+ uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
+ uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
+ char reg8_1aa[4];
+ uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
+ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
+ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
+ char res8_1b[2456];
+ uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */
+ uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */
+ uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */
+ uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */
+ char res8_1c[200];
uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
char res8_2[512];
uint debug_2;
uint debug_3;
uint debug_4;
- char res12[240];
+ uint debug_5;
+ uint debug_6;
+ uint debug_7;
+ uint debug_8;
+ uint debug_9;
+ uint debug_10;
+ uint debug_11;
+ uint debug_12;
+ uint debug_13; /* +0xF30 */
+ uint debug_14;
+ uint debug_15;
+ uint debug_16;
+ uint debug_17;
+ uint debug_18; /* +0xF44 */
+ char res12[184];
} ccsr_ddr_t;
/*
char res7[12];
uint lbcr; /* 0x50d0 - LBC Configuration Register */
uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
- char res8[12072];
+ char res8[3880];
} ccsr_lbc_t;
+/*
+ * eSPI Registers(0x7000-0x8000)
+ */
+typedef struct ccsr_espi {
+ uint mode; /* 0x00 - eSPI mode register */
+ uint event; /* 0x04 - eSPI event register */
+ uint mask; /* 0x08 - eSPI mask register */
+ uint com; /* 0x0c - eSPI command register */
+ uint tx; /* 0x10 - eSPI transmit FIFO access register */
+ uint rx; /* 0x14 - eSPI receive FIFO access register */
+ char res1[8]; /* reserved */
+ uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */
+ char res2[4048]; /* fill up to 0x1000 */
+} ccsr_espi_t;
+
/*
* PCI Registers(0x8000-0x9000)
*/
char res11[476];
} ccsr_pcix_t;
+typedef struct ccsr_gpio {
+ uint gpdir;
+ uint gpodr;
+ uint gpdat;
+ uint gpier;
+ uint gpimr;
+ uint gpicr;
+} ccsr_gpio_t;
+
#define PCIX_COMMAND 0x62
#define POWAR_EN 0x80000000
#define POWAR_IO_READ 0x00080000
char res15[420];
} ccsr_l2cache_t;
+#define MPC85xx_L2CTL_L2E 0x80000000
+#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
+#define MPC85xx_L2ERRDIS_MBECC 0x00000008
+#define MPC85xx_L2ERRDIS_SBECC 0x00000004
+
/*
* DMA Registers(0x2_1000-0x2_2000)
*/
typedef struct ccsr_dma {
char res1[256];
- uint mr0; /* 0x21100 - DMA 0 Mode Register */
- uint sr0; /* 0x21104 - DMA 0 Status Register */
- char res2[4];
- uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
- uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
- uint sar0; /* 0x21114 - DMA 0 Source Address Register */
- uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
- uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
- uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
- char res3[4];
- uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
- char res4[8];
- uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
- char res5[4];
- uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
- uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
- uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
- char res6[56];
- uint mr1; /* 0x21180 - DMA 1 Mode Register */
- uint sr1; /* 0x21184 - DMA 1 Status Register */
- char res7[4];
- uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
- uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
- uint sar1; /* 0x21194 - DMA 1 Source Address Register */
- uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
- uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
- uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
- char res8[4];
- uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
- char res9[8];
- uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
- char res10[4];
- uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
- uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
- uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
- char res11[56];
- uint mr2; /* 0x21200 - DMA 2 Mode Register */
- uint sr2; /* 0x21204 - DMA 2 Status Register */
- char res12[4];
- uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
- uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
- uint sar2; /* 0x21214 - DMA 2 Source Address Register */
- uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
- uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
- uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
- char res13[4];
- uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
- char res14[8];
- uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
- char res15[4];
- uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
- uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
- uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
- char res16[56];
- uint mr3; /* 0x21280 - DMA 3 Mode Register */
- uint sr3; /* 0x21284 - DMA 3 Status Register */
- char res17[4];
- uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
- uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
- uint sar3; /* 0x21294 - DMA 3 Source Address Register */
- uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
- uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
- uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
- char res18[4];
- uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
- char res19[8];
- uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
- char res20[4];
- uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
- uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
- uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
- char res21[56];
+ struct fsl_dma dma[4];
uint dgsr; /* 0x21300 - DMA General Status Register */
- char res22[11516];
+ char res2[11516];
} ccsr_dma_t;
/*
} ccsr_tsec_t;
/*
- * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
+ * PIC Registers(0x4_0000-0x8_0000)
*/
typedef struct ccsr_pic {
- char res0[106496]; /* 0x26000-0x40000 */
- char res1[64];
+ char res1[64]; /* 0x40000 */
uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
char res2[12];
uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
* 0x9000-0x90bff: General SIU
*/
typedef struct ccsr_cpm_siu {
- char res1[80];
+ char res1[80];
uint smaer;
uint smser;
uint smevr;
/* 0x91018-0x912ff: SDMA */
typedef struct ccsr_cpm_sdma {
uchar sdsr;
- char res1[3];
- uchar sdmr;
- char res2[739];
+ char res1[3];
+ uchar sdmr;
+ char res2[739];
} ccsr_cpm_sdma_t;
/* 0x91300-0x9131f: FCC1 */
/* 0x91400-0x915ef: TC layers */
typedef struct ccsr_cpm_tmp1 {
- char res[496];
+ char res[496];
} ccsr_cpm_tmp1_t;
/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
/* 0x91a80-0x91a9f */
typedef struct ccsr_cpm_tmp2 {
- char res[32];
+ char res[32];
} ccsr_cpm_tmp2_t;
/* 0x91aa0-0x91aff: SPI */
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
-#define im_dprambase im_dpram1
- u_char im_dpram1[16*1024];
- char res1[16*1024];
- u_char im_dpram2[16*1024];
- char res2[16*1024];
- ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
- ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
- ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
- ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
- ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
+#define im_dprambase im_dpram1
+ u_char im_dpram1[16*1024];
+ char res1[16*1024];
+ u_char im_dpram2[16*1024];
+ char res2[16*1024];
+ ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
+ ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
+ ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
+ ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
+ ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
ccsr_cpm_fcc1_t im_cpm_fcc1;
ccsr_cpm_fcc2_t im_cpm_fcc2;
ccsr_cpm_fcc3_t im_cpm_fcc3;
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
+#ifdef CONFIG_FSL_CORENET
+typedef struct ccsr_gur {
+ u32 porsr1; /* 0xe0000 - POR status register */
+ u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */
+ u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */
+ u8 res2[12];
+ u32 gpiocr; /* 0xe0030 - GPIO control register */
+ u8 res3[12];
+ u32 gpoutdr; /* 0xe0040 - General-purpose output data register */
+ u8 res4[12];
+ u32 gpindr; /* 0xe0050 - General-purpose input data register */
+ u8 res5[12];
+ u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+ u8 res6[12];
+ u32 devdisr; /* 0xe0070 - Device disable control */
+#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
+#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
+#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
+#define FSL_CORENET_DEVDISR_RMU 0x08000000
+#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
+#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
+#define FSL_CORENET_DEVDISR_DMA1 0x00400000
+#define FSL_CORENET_DEVDISR_DMA2 0x00200000
+#define FSL_CORENET_DEVDISR_DDR1 0x00100000
+#define FSL_CORENET_DEVDISR_DDR2 0x00080000
+#define FSL_CORENET_DEVDISR_DBG 0x00010000
+#define FSL_CORENET_DEVDISR_NAL 0x00008000
+#define FSL_CORENET_DEVDISR_ELBC 0x00001000
+#define FSL_CORENET_DEVDISR_USB1 0x00000800
+#define FSL_CORENET_DEVDISR_USB2 0x00000400
+#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
+#define FSL_CORENET_DEVDISR_GPIO 0x00000080
+#define FSL_CORENET_DEVDISR_ESPI 0x00000040
+#define FSL_CORENET_DEVDISR_I2C1 0x00000020
+#define FSL_CORENET_DEVDISR_I2C2 0x00000010
+#define FSL_CORENET_DEVDISR_DUART1 0x00000002
+#define FSL_CORENET_DEVDISR_DUART2 0x00000001
+ u8 res7[12];
+ u32 powmgtcsr; /* 0xe0080 - Power management status and control register */
+ u8 res8[12];
+ u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */
+ u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */
+ u8 res9[8];
+ u32 pvr; /* 0xe00a0 - Processor version register */
+ u32 svr; /* 0xe00a4 - System version register */
+ u8 res10[8];
+ u32 rstcr; /* 0xe00b0 - Reset control register */
+ u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */
+ u8 res11[8];
+ u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */
+ u8 res12[4]; /* Reserved: RSTRQMR2 */
+ u32 rstrqsr1; /* 0xe00c8 - Reset request status register */
+ u8 res13[4]; /* Reserved: RSTRQSR2 */
+ u8 res14[4]; /* Reserved: RSTRQWDTMRU */
+ u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */
+ u8 res15[4]; /* Reserved: RSTRQWDTSRU */
+ u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */
+ u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */
+ u32 brrl; /* 0xe00e4 Boot release register */
+ u8 res17[24];
+ u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */
+#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
+#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15
+#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
+ u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/
+ u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */
+ u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/
+ u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */
+ u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/
+ u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */
+ u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/
+ u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/
+ u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/
+ u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/
+ u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/
+ u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/
+ u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/
+ u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/
+ u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/
+ u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/
+ u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/
+ u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/
+ u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/
+ u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/
+ u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/
+ u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/
+ u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/
+ u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/
+ u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/
+ u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/
+ u8 res22[52]; /* Reserved: for future LIODN register expansion */
+ u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/
+ u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/
+ u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/
+ u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/
+ u8 res23[48]; /* Reserved: for future LIODN register expansion */
+ u8 res24[64]; /* Reserved */
+ u32 pblsr; /* 0xe0600 Preboot loader status register*/
+ u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/
+ u32 dmacr1; /* 0xe0608 DMA control register*/
+ u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/
+ u32 gensr1; /* 0xe0610 General status register*/
+ u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/
+ u32 gencr1; /* 0xe0620 General control register*/
+ u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/
+ u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */
+ u32 cgensrl; /* 0xe0634 Core general status register*/
+ u8 res29[8]; /* Reserved */
+ u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */
+ u32 cgencrl; /* 0xe0634 Core general control register*/
+ u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */
+ u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/
+ u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */
+} ccsr_gur_t;
+
+typedef struct ccsr_clk {
+ u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */
+ u8 res1[0x1c];
+ u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */
+ u8 res2[0x1c];
+ u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */
+ u8 res3[0x1c];
+ u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */
+ u8 res4[0x1c];
+ u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */
+ u8 res5[0x1c];
+ u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */
+ u8 res6[0x1c];
+ u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */
+ u8 res7[0x1c];
+ u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */
+ u8 res8[0x71c];
+ u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */
+ u8 res10[0x1c];
+ u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */
+ u8 res11[0x1c];
+ u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */
+ u8 res12[0x1c];
+ u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */
+ u8 res13[0x39c];
+ u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */
+ u8 res14[0x1c];
+ u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */
+ u8 res15[0x3dc];
+} ccsr_clk_t;
+
+typedef struct ccsr_rcpm {
+ u8 res1[4]; /* 0xe2000 - Reserved */
+ u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */
+ u8 res2[4]; /* 0xe2008 - Reserved */
+ u32 cdozcrl; /* 0xe200c - Core Doze Control Register */
+ u8 res3[4]; /* 0xe2010 - Reserved */
+ u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */
+ u8 res4[4]; /* 0xe2018 - Reserved */
+ u32 cnapcrl; /* 0xe201c - Core Nap Control Register */
+ u8 res5[4]; /* 0xe2020 - Reserved */
+ u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */
+ u8 res6[4]; /* 0xe2028 - Reserved */
+ u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */
+ u8 res7[4]; /* 0xe2030 - Reserved */
+ u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */
+ u8 res8[8]; /* Reserved */
+ u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */
+ u8 res9[12]; /* Reserved */
+ u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */
+ u8 res10[12]; /* Reserved */
+ u8 res11[4]; /* Reserved */
+ u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */
+ u8 res12[4]; /* Reserved */
+ u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */
+ u8 res13[4]; /* Reserved */
+ u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */
+ u8 res14[4]; /* Reserved */
+ u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */
+ u8 res15[4]; /* Reserved */
+ u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */
+ u8 res16[4]; /* Reserved */
+ u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */
+ u8 res17[4]; /* Reserved */
+ u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */
+ u8 res18[0xf68];
+} ccsr_rcpm_t;
+
+#else
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
+#ifdef CONFIG_MPC8536
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
+#else
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
+#endif
+#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
+#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
+#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
+#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
uint porbmsr; /* 0xe0004 - POR boot mode status register */
-#define MPC85xx_PORBMSR_HA 0x00070000
+#define MPC85xx_PORBMSR_HA 0x00070000
+#define MPC85xx_PORBMSR_HA_SHIFT 16
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
-#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
-#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
-#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
-#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
-#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
-#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
+#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
+#define MPC85xx_PORDEVSR_PCI1 0x00800000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
+#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
-#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
+#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
- char res1[12];
+ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
+/* The 8544 RM says this is bit 26, but it's really bit 24 */
+#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
+ char res1[8];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
char res2[12];
uint gpiocr; /* 0xe0030 - GPIO control register */
char res3[12];
+#if defined(CONFIG_MPC8569)
+ uint plppar1;
+ /* 0xe0040 - Platform port pin assignment register 1 */
+ uint plppar2;
+ /* 0xe0044 - Platform port pin assignment register 2 */
+ uint plpdir1;
+ /* 0xe0048 - Platform port pin direction register 1 */
+ uint plpdir2;
+ /* 0xe004c - Platform port pin direction register 2 */
+#else
uint gpoutdr; /* 0xe0040 - General-purpose output data register */
char res4[12];
+#endif
uint gpindr; /* 0xe0050 - General-purpose input data register */
char res5[12];
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_SD_DATA 0x80000000
+#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
+#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
#define MPC85xx_DEVDISR_SEC 0x01000000
#define MPC85xx_DEVDISR_SRIO 0x00080000
#define MPC85xx_DEVDISR_RMSG 0x00040000
-#define MPC85xx_DEVDISR_DDR 0x00010000
-#define MPC85xx_DEVDISR_CPU 0x00008000
-#define MPC85xx_DEVDISR_TB 0x00004000
+#define MPC85xx_DEVDISR_DDR 0x00010000
+#define MPC85xx_DEVDISR_CPU 0x00008000
+#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
+#define MPC85xx_DEVDISR_TB 0x00004000
+#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1 0x00002000
+#define MPC85xx_DEVDISR_TB1 0x00001000
#define MPC85xx_DEVDISR_DMA 0x00000400
#define MPC85xx_DEVDISR_TSEC1 0x00000080
#define MPC85xx_DEVDISR_TSEC2 0x00000040
uint svr; /* 0xe00a4 - System version register */
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
-#ifdef CONFIG_MPC8568
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
char res10b[76];
par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
char res10c[3136];
uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
- uint res14; /* 0xe0f28 */
+ uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
+#endif
-#define CFG_MPC85xx_GUTS_OFFSET (0xE0000)
-#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
-
-#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
+#ifdef CONFIG_FSL_CORENET
+#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
+#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
+#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000
+#define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000
+#else
+#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
+#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
+#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
+#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
+#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
+#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
+#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
+#endif
-typedef struct immap {
- ccsr_local_ecm_t im_local_ecm;
- ccsr_ddr_t im_ddr;
- ccsr_i2c_t im_i2c;
- ccsr_duart_t im_duart;
- ccsr_lbc_t im_lbc;
- ccsr_pcix_t im_pcix;
- ccsr_pcix_t im_pcix2;
- char reserved[90112];
- ccsr_l2cache_t im_l2cache;
- ccsr_dma_t im_dma;
- ccsr_tsec_t im_tsec1;
- ccsr_tsec_t im_tsec2;
- ccsr_pic_t im_pic;
- ccsr_cpm_t im_cpm;
-} immap_t;
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
+#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
-extern immap_t *immr;
+#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET)
+#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET)
+#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
+#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
+#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
+#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
+#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
+#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
+#define CONFIG_SYS_MPC85xx_USB_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
#endif /*__IMMAP_85xx__*/
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