unsigned long cpm_clk;
unsigned long scc_clk;
unsigned long brg_clk;
+#ifdef CONFIG_PCI
+ unsigned long pci_clk;
+#endif
#endif
unsigned long mem_clk;
#if defined(CONFIG_MPC83XX)
#endif /* CONFIG_MPC834X */
#if defined(CONFIG_MPC8315)
u32 tdm_clk;
-#endif
-#if defined(CONFIG_MPC837X)
- u32 sdhc_clk;
#endif
u32 core_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
- u32 ddr_clk;
u32 pci_clk;
#if defined(CONFIG_MPC837X)
u32 pciexp1_clk;
u32 sata_clk;
#endif
#if defined(CONFIG_MPC8360)
- u32 ddr_sec_clk;
+ u32 mem_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536)
+ u32 sdhc_clk;
+#endif
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 i2c1_clk;
u32 i2c2_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
+#if defined(CONFIG_FSL_LAW)
+ u32 used_laws;
+#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
unsigned long pev_clk;
unsigned long flb_clk;
#endif
- unsigned long ram_size; /* RAM size */
+ phys_size_t ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long reset_status; /* reset status register at boot */
+#if defined(CONFIG_MPC83XX)
+ unsigned long arbiter_event_attributes;
+ unsigned long arbiter_event_address;
+#endif
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
#endif
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
+#endif
+#if defined(CONFIG_WD_MAX_RATE)
+ unsigned long long wdt_last; /* trace watch-dog triggering rate */
#endif
void **jt; /* jump table */
} gd_t;
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")