#define SDRAMC_DMRn_WP (0x00000100)
#define SDRAMC_DMRn_V (0x00000001)
-/*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-/* Bit definitions and macros for FBCS_CSMR */
-#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
-#define FBCS_CSMR_BAM_4G (0xFFFF0000)
-#define FBCS_CSMR_BAM_2G (0x7FFF0000)
-#define FBCS_CSMR_BAM_1G (0x3FFF0000)
-#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
-#define FBCS_CSMR_BAM_512M (0x1FFF0000)
-#define FBCS_CSMR_BAM_256M (0x0FFF0000)
-#define FBCS_CSMR_BAM_128M (0x07FF0000)
-#define FBCS_CSMR_BAM_64M (0x03FF0000)
-#define FBCS_CSMR_BAM_32M (0x01FF0000)
-#define FBCS_CSMR_BAM_16M (0x00FF0000)
-#define FBCS_CSMR_BAM_8M (0x007F0000)
-#define FBCS_CSMR_BAM_4M (0x003F0000)
-#define FBCS_CSMR_BAM_2M (0x001F0000)
-#define FBCS_CSMR_BAM_1M (0x000F0000)
-#define FBCS_CSMR_BAM_1024K (0x000F0000)
-#define FBCS_CSMR_BAM_512K (0x00070000)
-#define FBCS_CSMR_BAM_256K (0x00030000)
-#define FBCS_CSMR_BAM_128K (0x00010000)
-#define FBCS_CSMR_BAM_64K (0x00000000)
-#define FBCS_CSMR_WP (0x00000100)
-#define FBCS_CSMR_V (0x00000001)
-
-/* Bit definitions and macros for FBCS_CSCR */
-#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
-#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
-#define FBCS_CSCR_AA (0x0100)
-#define FBCS_CSCR_PS_MASK (0x00C0)
-#define FBCS_CSCR_PS_32 (0x0000)
-#define FBCS_CSCR_PS_16 (0x0080)
-#define FBCS_CSCR_PS_8 (0x0040)
-#define FBCS_CSCR_BEM (0x0020)
-#define FBCS_CSCR_BSTR (0x0010)
-#define FBCS_CSCR_BSTW (0x0008)
-#define FBCS_CSCR_SWWS(x) ((x)&0x07)
-
-/*********************************************************************
-* Queued Serial Peripheral Interface (QSPI)
-*********************************************************************/
-/* Bit definitions and macros for QSPI_QMR */
-#define QSPI_QMR_MSTR (0x8000)
-#define QSPI_QMR_DOHIE (0x4000)
-#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
-#define QSPI_QMR_CPOL (0x0200)
-#define QSPI_QMR_CPHA (0x0100)
-#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QDLYR */
-#define QSPI_QDLYR_SPE (0x8000)
-#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
-#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QWR */
-#define QSPI_QWR_HALT (0x8000)
-#define QSPI_QWR_WREN (0x4000)
-#define QSPI_QWR_WRTO (0x2000)
-#define QSPI_QWR_CSIV (0x1000)
-#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
-#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
-
-/* Bit definitions and macros for QSPI_QIR */
-#define QSPI_QIR_WCEFB (0x8000)
-#define QSPI_QIR_ABRTB (0x4000)
-#define QSPI_QIR_ABRTL (0x1000)
-#define QSPI_QIR_WCEFE (0x0800)
-#define QSPI_QIR_ABRTE (0x0400)
-#define QSPI_QIR_SPIFE (0x0100)
-#define QSPI_QIR_WCEF (0x0008)
-#define QSPI_QIR_ABRT (0x0004)
-#define QSPI_QIR_SPIF (0x0001)
-
-/* Bit definitions and macros for QSPI_QAR */
-#define QSPI_QAR_ADDR(x) ((x)&0x003F)
-
-/* Bit definitions and macros for QSPI_QDR */
-#define QSPI_QDR_CONT (0x8000)
-#define QSPI_QDR_BITSE (0x4000)
-#define QSPI_QDR_DT (0x2000)
-#define QSPI_QDR_DSCK (0x1000)
-#define QSPI_QDR_QSPI_CS3 (0x0800)
-#define QSPI_QDR_QSPI_CS2 (0x0400)
-#define QSPI_QDR_QSPI_CS1 (0x0200)
-#define QSPI_QDR_QSPI_CS0 (0x0100)
-
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT1_HI_ETPU_TC31F (58)
#define INT1_HI_ETPU_TGIF (59)
-/* Bit definitions and macros for INTC_IPRH */
-#define INTC_IPRH_INT63 (0x80000000)
-#define INTC_IPRH_INT62 (0x40000000)
-#define INTC_IPRH_INT61 (0x20000000)
-#define INTC_IPRH_INT60 (0x10000000)
-#define INTC_IPRH_INT59 (0x08000000)
-#define INTC_IPRH_INT58 (0x04000000)
-#define INTC_IPRH_INT57 (0x02000000)
-#define INTC_IPRH_INT56 (0x01000000)
-#define INTC_IPRH_INT55 (0x00800000)
-#define INTC_IPRH_INT54 (0x00400000)
-#define INTC_IPRH_INT53 (0x00200000)
-#define INTC_IPRH_INT52 (0x00100000)
-#define INTC_IPRH_INT51 (0x00080000)
-#define INTC_IPRH_INT50 (0x00040000)
-#define INTC_IPRH_INT49 (0x00020000)
-#define INTC_IPRH_INT48 (0x00010000)
-#define INTC_IPRH_INT47 (0x00008000)
-#define INTC_IPRH_INT46 (0x00004000)
-#define INTC_IPRH_INT45 (0x00002000)
-#define INTC_IPRH_INT44 (0x00001000)
-#define INTC_IPRH_INT43 (0x00000800)
-#define INTC_IPRH_INT42 (0x00000400)
-#define INTC_IPRH_INT41 (0x00000200)
-#define INTC_IPRH_INT40 (0x00000100)
-#define INTC_IPRH_INT39 (0x00000080)
-#define INTC_IPRH_INT38 (0x00000040)
-#define INTC_IPRH_INT37 (0x00000020)
-#define INTC_IPRH_INT36 (0x00000010)
-#define INTC_IPRH_INT35 (0x00000008)
-#define INTC_IPRH_INT34 (0x00000004)
-#define INTC_IPRH_INT33 (0x00000002)
-#define INTC_IPRH_INT32 (0x00000001)
-
-/* Bit definitions and macros for INTC_IPRL */
-#define INTC_IPRL_INT31 (0x80000000)
-#define INTC_IPRL_INT30 (0x40000000)
-#define INTC_IPRL_INT29 (0x20000000)
-#define INTC_IPRL_INT28 (0x10000000)
-#define INTC_IPRL_INT27 (0x08000000)
-#define INTC_IPRL_INT26 (0x04000000)
-#define INTC_IPRL_INT25 (0x02000000)
-#define INTC_IPRL_INT24 (0x01000000)
-#define INTC_IPRL_INT23 (0x00800000)
-#define INTC_IPRL_INT22 (0x00400000)
-#define INTC_IPRL_INT21 (0x00200000)
-#define INTC_IPRL_INT20 (0x00100000)
-#define INTC_IPRL_INT19 (0x00080000)
-#define INTC_IPRL_INT18 (0x00040000)
-#define INTC_IPRL_INT17 (0x00020000)
-#define INTC_IPRL_INT16 (0x00010000)
-#define INTC_IPRL_INT15 (0x00008000)
-#define INTC_IPRL_INT14 (0x00004000)
-#define INTC_IPRL_INT13 (0x00002000)
-#define INTC_IPRL_INT12 (0x00001000)
-#define INTC_IPRL_INT11 (0x00000800)
-#define INTC_IPRL_INT10 (0x00000400)
-#define INTC_IPRL_INT9 (0x00000200)
-#define INTC_IPRL_INT8 (0x00000100)
-#define INTC_IPRL_INT7 (0x00000080)
-#define INTC_IPRL_INT6 (0x00000040)
-#define INTC_IPRL_INT5 (0x00000020)
-#define INTC_IPRL_INT4 (0x00000010)
-#define INTC_IPRL_INT3 (0x00000008)
-#define INTC_IPRL_INT2 (0x00000004)
-#define INTC_IPRL_INT1 (0x00000002)
-#define INTC_IPRL_INT0 (0x00000001)
-
-/* Bit definitions and macros for INTC_IRLR */
-#define INTC_IRLRn(x) (((x)&0x7F)<<1)
-
-/* Bit definitions and macros for INTC_IACKLPRn */
-#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
-#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
-
-/* Bit definitions and macros for INTC_ICRnx */
-#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
-#define INTC_ICRnx_IP(x) ((x)&0x07)
-
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
#define PLL_SYNSR_CALDONE (0x00000002)
#define PLL_SYNSR_CALPASS (0x00000001)
-/*********************************************************************
- * Edge Port
-*********************************************************************/
-#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
-#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
-#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
-#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
-#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
-#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
-#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
-
-#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
-#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
-#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
-#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
-#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
-#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
-#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
-
-#define EPORT_EPIER_EPIE7 (0x80)
-#define EPORT_EPIER_EPIE6 (0x40)
-#define EPORT_EPIER_EPIE5 (0x20)
-#define EPORT_EPIER_EPIE4 (0x10)
-#define EPORT_EPIER_EPIE3 (0x08)
-#define EPORT_EPIER_EPIE2 (0x04)
-#define EPORT_EPIER_EPIE1 (0x02)
-
-#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
-#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
-#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
-#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
-#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
-#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
-#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
-
-#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
-#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
-#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
-#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
-#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
-#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
-#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
-
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_EN (0x0001)
-/*********************************************************************
-* FlexCAN Module (CAN)
-*********************************************************************/
-/* Bit definitions and macros for CAN_CANMCR */
-#define CANMCR_MDIS (0x80000000)
-#define CANMCR_FRZ (0x40000000)
-#define CANMCR_HALT (0x10000000)
-#define CANMCR_NORDY (0x08000000)
-#define CANMCR_SOFTRST (0x02000000)
-#define CANMCR_FRZACK (0x01000000)
-#define CANMCR_SUPV (0x00800000)
-#define CANMCR_LPMACK (0x00100000)
-#define CANMCR_MAXMB(x) (((x)&0x0F))
-
-/* Bit definitions and macros for CAN_CANCTRL */
-#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
-#define CANCTRL_RJW(x) (((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK (0x00008000)
-#define CANCTRL_ERRMSK (0x00004000)
-#define CANCTRL_CLKSRC (0x00002000)
-#define CANCTRL_LPB (0x00001000)
-#define CANCTRL_SMP (0x00000080)
-#define CANCTRL_BOFFREC (0x00000040)
-#define CANCTRL_TSYNC (0x00000020)
-#define CANCTRL_LBUF (0x00000010)
-#define CANCTRL_LOM (0x00000008)
-#define CANCTRL_PROPSEG(x) (((x)&0x07))
-
-/* Bit definitions and macros for CAN_TIMER */
-#define TIMER_TIMER(x) ((x)&0xFFFF)
-
-/* Bit definitions and macros for CAN_RXGMASK */
-#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
-
-/* Bit definitions and macros for CAN_ERRCNT */
-#define ERRCNT_TXECTR(x) (((x)&0xFF))
-#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
-
-/* Bit definitions and macros for CAN_ERRSTAT */
-#define ERRSTAT_BITERR1 (0x00008000)
-#define ERRSTAT_BITERR0 (0x00004000)
-#define ERRSTAT_ACKERR (0x00002000)
-#define ERRSTAT_CRCERR (0x00001000)
-#define ERRSTAT_FRMERR (0x00000800)
-#define ERRSTAT_STFERR (0x00000400)
-#define ERRSTAT_TXWRN (0x00000200)
-#define ERRSTAT_RXWRN (0x00000100)
-#define ERRSTAT_IDLE (0x00000080)
-#define ERRSTAT_TXRX (0x00000040)
-#define ERRSTAT_FLT_BUSOFF (0x00000020)
-#define ERRSTAT_FLT_PASSIVE (0x00000010)
-#define ERRSTAT_FLT_ACTIVE (0x00000000)
-#define ERRSTAT_BOFFINT (0x00000004)
-#define ERRSTAT_ERRINT (0x00000002)
-
-/* Bit definitions and macros for CAN_IMASK */
-#define IMASK_BUF15M (0x00008000)
-#define IMASK_BUF14M (0x00004000)
-#define IMASK_BUF13M (0x00002000)
-#define IMASK_BUF12M (0x00001000)
-#define IMASK_BUF11M (0x00000800)
-#define IMASK_BUF10M (0x00000400)
-#define IMASK_BUF9M (0x00000200)
-#define IMASK_BUF8M (0x00000100)
-#define IMASK_BUF7M (0x00000080)
-#define IMASK_BUF6M (0x00000040)
-#define IMASK_BUF5M (0x00000020)
-#define IMASK_BUF4M (0x00000010)
-#define IMASK_BUF3M (0x00000008)
-#define IMASK_BUF2M (0x00000004)
-#define IMASK_BUF1M (0x00000002)
-#define IMASK_BUF0M (0x00000001)
-
-/* Bit definitions and macros for CAN_IFLAG */
-#define IFLAG_BUF15I (0x00008000)
-#define IFLAG_BUF14I (0x00004000)
-#define IFLAG_BUF13I (0x00002000)
-#define IFLAG_BUF12I (0x00001000)
-#define IFLAG_BUF11I (0x00000800)
-#define IFLAG_BUF10I (0x00000400)
-#define IFLAG_BUF9I (0x00000200)
-#define IFLAG_BUF8I (0x00000100)
-#define IFLAG_BUF7I (0x00000080)
-#define IFLAG_BUF6I (0x00000040)
-#define IFLAG_BUF5I (0x00000020)
-#define IFLAG_BUF4I (0x00000010)
-#define IFLAG_BUF3I (0x00000008)
-#define IFLAG_BUF2I (0x00000004)
-#define IFLAG_BUF1I (0x00000002)
-#define IFLAG_BUF0I (0x00000001)
-
#endif /* mcf5235_h */
projects / oweals / u-boot.git / blobdiff