arm: Kirkwood: Correct header define

[oweals/u-boot.git] / include / asm-blackfin / mach-bf548 / ADSP-EDN-BF542-extended_cdef.h

diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
index e9572a0b005b55a82b22010eac07d59a06c4c169..51d9cf240aa18d457abdbb4a9dece610e97d4ac6 100644 (file)
--- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
@@ -3577,7 +3577,6 @@
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
 #define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
 #define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
@@ -3643,7 +3642,6 @@
 #define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
 #define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
 #define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX()          bfin_read32(SPORT2_TX)
 #define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
 #define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
 #define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
@@ -3709,7 +3707,6 @@
 #define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
 #define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
 #define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX()          bfin_read32(SPORT3_TX)
 #define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
 #define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
 #define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)