ahci: add defines for PORT_SCR_STAT register bits

[oweals/u-boot.git] / include / ahci.h

diff --git a/include/ahci.h b/include/ahci.h
index 0c6bbbdc56c8180daa9ad453472c077dff229d56..d76993ca2a2880e02aeb8f4e0c86a9cc08b63b0e 100644 (file)
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -3,37 +3,23 @@
  * Author: Jason Jin<Jason.jin@freescale.com>
  *         Zhang Wei<wei.zhang@freescale.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _AHCI_H_
 #define _AHCI_H_
 
+#include <pci.h>
+
 #define AHCI_PCI_BAR           0x24
 #define AHCI_MAX_SG            56 /* hardware max is 64K */
 #define AHCI_CMD_SLOT_SZ       32
+#define AHCI_MAX_CMD_SLOT      32
 #define AHCI_RX_FIS_SZ         256
 #define AHCI_CMD_TBL_HDR       0x80
 #define AHCI_CMD_TBL_CDB       0x40
 #define AHCI_CMD_TBL_SZ                AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
-#define AHCI_PORT_PRIV_DMA_SZ  AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ      \
-                               + AHCI_RX_FIS_SZ
+#define AHCI_PORT_PRIV_DMA_SZ  (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+                               AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
 #define AHCI_CMD_ATAPI         (1 << 5)
 #define AHCI_CMD_WRITE         (1 << 6)
 #define AHCI_CMD_PREFETCH      (1 << 7)
@@ -48,6 +34,7 @@
 #define HOST_IRQ_STAT          0x08 /* interrupt status */
 #define HOST_PORTS_IMPL                0x0c /* bitmap of implemented ports */
 #define HOST_VERSION           0x10 /* AHCI spec. version compliancy */
+#define HOST_CAP2              0x24 /* host capabilities, extended */
 
 /* HOST_CTL bits */
 #define HOST_RESET             (1 << 0)  /* reset controller; self-clear */
@@ -100,6 +87,11 @@
                                | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
                                | PORT_IRQ_D2H_REG_FIS
 
+/* PORT_SCR_STAT bits */
+#define PORT_SCR_STAT_DET_MASK 0x3
+#define PORT_SCR_STAT_DET_COMINIT 0x1
+#define PORT_SCR_STAT_DET_PHYRDY 0x3
+
 /* PORT_CMD bits */
 #define PORT_CMD_ATAPI         (1 << 24) /* Device is ATAPI */
 #define PORT_CMD_LIST_ON       (1 << 15) /* cmd list DMA engine running */
@@ -187,4 +179,6 @@ struct ahci_probe_ent {
        u32     link_port_map; /*linkup port map*/
 };
 
+int ahci_init(u32 base);
+
 #endif