mmc: fsl_esdhc: workaround for hardware 3.3v IO reliability issue

[oweals/u-boot.git] / drivers / video / videomodes.c

diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index 6d96b33f20d0f2e532b77c70e0c177b663da9eaa..89003eea7276972b202abe9a56c622b7e21336a5 100644 (file)
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2004
  * Pierre Aubert, Staubli Faverges , <p.aubert@staubli.com>
  * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /************************************************************************
@@ -59,6 +58,7 @@
 
 #include <common.h>
 #include <edid.h>
+#include <env.h>
 #include <errno.h>
 #include <linux/ctype.h>
 
@@ -397,10 +397,8 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
            EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*t) == 0 ||
            EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 ||
            EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 ||
-           EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*t) == 0 ||
            EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 ||
-           EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*t) == 0 ||
-           /* 3d formats are not supported*/
+           /* 3d formats are not supported */
            EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0)
                return -EINVAL;
 
@@ -446,3 +444,32 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
 
        return 0;
 }
+
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+                                      struct display_timing *timing)
+{
+       timing->pixelclock.typ = mode->pixclock_khz * 1000;
+
+       timing->hactive.typ = mode->xres;
+       timing->hfront_porch.typ = mode->right_margin;
+       timing->hback_porch.typ = mode->left_margin;
+       timing->hsync_len.typ = mode->hsync_len;
+
+       timing->vactive.typ = mode->yres;
+       timing->vfront_porch.typ = mode->lower_margin;
+       timing->vback_porch.typ = mode->upper_margin;
+       timing->vsync_len.typ = mode->vsync_len;
+
+       timing->flags = 0;
+
+       if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+               timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+       else
+               timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
+       if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+               timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+       else
+               timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
+       if (mode->vmode == FB_VMODE_INTERLACED)
+               timing->flags |= DISPLAY_FLAGS_INTERLACED;
+}