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Merge branch '2020-05-18-reduce-size-of-common.h'
[oweals/u-boot.git] / drivers / video / tegra124 / dp.c
diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c
index 3c0b721e3b8226d024d39a31270ceed2d69fab2d..59758eb93614f1717bddee5bee2e0f7736e5b6d3 100644 (file)
--- a/drivers/video/tegra124/dp.c
+++ b/drivers/video/tegra124/dp.c
@@ -1,23 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2011-2013, NVIDIA Corporation.
  * Copyright 2014 Google Inc.
- *
- * SPDX-License-Identifier:     GPL-2.0
  */
 
 #include <common.h>
-#include <displayport.h>
+#include <display.h>
 #include <dm.h>
 #include <div64.h>
 #include <errno.h>
-#include <fdtdec.h>
+#include <log.h>
+#include <video_bridge.h>
 #include <asm/io.h>
 #include <asm/arch-tegra/dc.h>
-#include "displayport.h"
+#include <linux/delay.h>
+#include "display.h"
 #include "edid.h"
 #include "sor.h"
-
-DECLARE_GLOBAL_DATA_PTR;
+#include "displayport.h"
 
 #define DO_FAST_LINK_TRAINING          1
 
@@ -25,9 +25,15 @@ struct tegra_dp_plat {
        ulong base;
 };
 
+/**
+ * struct tegra_dp_priv - private displayport driver info
+ *
+ * @dc_dev:    Display controller device that is sending the video feed
+ */
 struct tegra_dp_priv {
+       struct udevice *sor;
+       struct udevice *dc_dev;
        struct dpaux_ctlr *regs;
-       struct tegra_dc_sor_data *sor;
        u8 revision;
        int enabled;
 };
@@ -709,8 +715,8 @@ static int tegra_dc_dp_init_max_link_cfg(
        return 0;
 }
 
-static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp,
-                               struct tegra_dc_sor_data *sor, int ena)
+static int tegra_dc_dp_set_assr(struct tegra_dp_priv *priv,
+                               struct udevice *sor, int ena)
 {
        int ret;
 
@@ -718,7 +724,7 @@ static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp,
                DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE :
                DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE;
 
-       ret = tegra_dc_dp_dpcd_write(dp, DP_EDP_CONFIGURATION_SET,
+       ret = tegra_dc_dp_dpcd_write(priv, DP_EDP_CONFIGURATION_SET,
                                     dpcd_data);
        if (ret)
                return ret;
@@ -729,7 +735,7 @@ static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp,
 }
 
 static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp,
-                                      struct tegra_dc_sor_data *sor,
+                                      struct udevice *sor,
                                       u8 link_bw)
 {
        tegra_dc_sor_set_link_bandwidth(sor, link_bw);
@@ -740,7 +746,7 @@ static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp,
 
 static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp,
                const struct tegra_dp_link_config *link_cfg,
-               struct tegra_dc_sor_data *sor)
+               struct udevice *sor)
 {
        u8      dpcd_data;
        int     ret;
@@ -1001,7 +1007,7 @@ fail:
 static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],
                              u32 pc[4], const struct tegra_dp_link_config *cfg)
 {
-       struct tegra_dc_sor_data *sor = dp->sor;
+       struct udevice *sor = dp->sor;
        u32 n_lanes = cfg->lane_count;
        u8 pc_supported = cfg->tps3_supported;
        u32 cnt;
@@ -1185,7 +1191,7 @@ static int tegra_dc_dp_full_link_training(struct tegra_dp_priv *dp,
                                          const struct display_timing *timing,
                                          struct tegra_dp_link_config *cfg)
 {
-       struct tegra_dc_sor_data *sor = dp->sor;
+       struct udevice *sor = dp->sor;
        int err;
        u32 pe[4], vs[4], pc[4];
 
@@ -1228,7 +1234,7 @@ fail:
  */
 static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp,
                const struct tegra_dp_link_config *link_cfg,
-               struct tegra_dc_sor_data *sor)
+               struct udevice *sor)
 {
        u8      link_bw;
        u8      lane_count;
@@ -1300,7 +1306,7 @@ static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp,
 static int tegra_dp_do_link_training(struct tegra_dp_priv *dp,
                struct tegra_dp_link_config *link_cfg,
                const struct display_timing *timing,
-               struct tegra_dc_sor_data *sor)
+               struct udevice *sor)
 {
        u8      link_bw;
        u8      lane_count;
@@ -1343,7 +1349,7 @@ static int tegra_dp_do_link_training(struct tegra_dp_priv *dp,
 
 static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp,
                        struct tegra_dp_link_config *link_cfg,
-                       struct tegra_dc_sor_data *sor,
+                       struct udevice *sor,
                        const struct display_timing *timing)
 {
        struct tegra_dp_link_config temp_cfg;
@@ -1443,7 +1449,7 @@ static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp,
                        printf("DP: Out of sync after %d retries\n", max_retry);
                        return -EIO;
                }
-               ret = tegra_dc_sor_detach(dp->sor);
+               ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor);
                if (ret)
                        return ret;
                if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor,
@@ -1453,7 +1459,7 @@ static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp,
                }
 
                tegra_dc_sor_set_power_state(dp->sor, 1);
-               tegra_dc_sor_attach(dp->sor, link_cfg, timing);
+               tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing);
 
                /* Increase delay_frame for next try in case the sink is
                   skipping more frames */
@@ -1466,7 +1472,7 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp,
 {
        struct tegra_dp_priv *priv = dev_get_priv(dev);
        struct tegra_dp_link_config slink_cfg, *link_cfg = &slink_cfg;
-       struct tegra_dc_sor_data *sor;
+       struct udevice *sor;
        int data;
        int retry;
        int ret;
@@ -1488,9 +1494,11 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp,
                return -ENOLINK;
        }
 
-       ret = tegra_dc_sor_init(&sor);
-       if (ret)
+       ret = uclass_first_device(UCLASS_VIDEO_BRIDGE, &sor);
+       if (ret || !sor) {
+               debug("dp: failed to find SOR device: ret=%d\n", ret);
                return ret;
+       }
        priv->sor = sor;
        ret = tegra_dc_sor_enable_dp(sor, link_cfg);
        if (ret)
@@ -1530,7 +1538,7 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp,
        }
 
        tegra_dc_sor_set_power_state(sor, 1);
-       ret = tegra_dc_sor_attach(sor, link_cfg, timing);
+       ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing);
        if (ret && ret != -EEXIST)
                return ret;
 
@@ -1547,6 +1555,12 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp,
        /* Power down the unused lanes to save power - a few hundred mW */
        tegra_dc_sor_power_down_unused_lanes(sor, link_cfg);
 
+       ret = video_bridge_set_backlight(sor, 80);
+       if (ret) {
+               debug("dp: failed to set backlight\n");
+               return ret;
+       }
+
        priv->enabled = true;
 error_enable:
        return 0;
@@ -1555,9 +1569,8 @@ error_enable:
 static int tegra_dp_ofdata_to_platdata(struct udevice *dev)
 {
        struct tegra_dp_plat *plat = dev_get_platdata(dev);
-       const void *blob = gd->fdt_blob;
 
-       plat->base = fdtdec_get_addr(blob, dev->of_offset, "reg");
+       plat->base = dev_read_addr(dev);
 
        return 0;
 }
@@ -1574,7 +1587,7 @@ static int tegra_dp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
                                     buf_size, &aux_stat);
 }
 
-static const struct dm_display_port_ops dp_tegra_ops = {
+static const struct dm_display_ops dp_tegra_ops = {
        .read_edid = tegra_dp_read_edid,
        .enable = tegra_dp_enable,
 };
@@ -1583,10 +1596,14 @@ static int dp_tegra_probe(struct udevice *dev)
 {
        struct tegra_dp_plat *plat = dev_get_platdata(dev);
        struct tegra_dp_priv *priv = dev_get_priv(dev);
+       struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
 
        priv->regs = (struct dpaux_ctlr *)plat->base;
        priv->enabled = false;
 
+       /* Remember the display controller that is sending us video */
+       priv->dc_dev = disp_uc_plat->src_dev;
+
        return 0;
 }
 
@@ -1597,7 +1614,7 @@ static const struct udevice_id tegra_dp_ids[] = {
 
 U_BOOT_DRIVER(dp_tegra) = {
        .name   = "dpaux_tegra",
-       .id     = UCLASS_DISPLAY_PORT,
+       .id     = UCLASS_DISPLAY,
        .of_match = tegra_dp_ids,
        .ofdata_to_platdata = tegra_dp_ofdata_to_platdata,
        .probe  = dp_tegra_probe,
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