* Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
*/
#include <common.h>
+#include <dm.h>
+#include <env.h>
#include <linux/errno.h>
#include <malloc.h>
+#include <video.h>
#include <video_fb.h>
#include <asm/arch/clock.h>
#include "videomodes.h"
#define PS2KHZ(ps) (1000000000UL / (ps))
+#define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
+
+#define BITS_PP 18
+#define BYTES_PP 4
-static GraphicDevice panel;
struct mxs_dma_desc desc;
/**
writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
}
-static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, void *fb)
+static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
{
/* Start framebuffer */
- mxs_lcd_init((u32)fb, mode, bpp);
+ mxs_lcd_init(fb, mode, bpp);
#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
/*
return 0;
}
-void lcdif_power_down(void)
+static int mxs_remove_common(u32 fb)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
int timeout = 1000000;
- if (!panel.frameAdrs)
- return;
+ if (!fb)
+ return -EINVAL;
- writel(panel.frameAdrs, ®s->hw_lcdif_cur_buf_reg);
- writel(panel.frameAdrs, ®s->hw_lcdif_next_buf_reg);
+ writel(fb, ®s->hw_lcdif_cur_buf_reg);
+ writel(fb, ®s->hw_lcdif_next_buf_reg);
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
while (--timeout) {
if (readl(®s->hw_lcdif_ctrl1_reg) &
udelay(1);
}
mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_VIDEO
+
+static GraphicDevice panel;
+
+void lcdif_power_down(void)
+{
+ mxs_remove_common(panel.frameAdrs);
}
void *video_hw_init(void)
printf("%s\n", panel.modeIdent);
- ret = mxs_probe_common(&mode, bpp, fb);
+ ret = mxs_probe_common(&mode, bpp, (u32)fb);
if (ret)
goto dealloc_fb;
return NULL;
}
+#else /* ifndef CONFIG_DM_VIDEO */
+
+static int mxs_of_get_timings(struct udevice *dev,
+ struct display_timing *timings,
+ u32 *bpp)
+{
+ int ret = 0;
+ u32 display_phandle;
+ ofnode display_node;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
+ if (ret) {
+ dev_err(dev, "required display property isn't provided\n");
+ return -EINVAL;
+ }
+
+ display_node = ofnode_get_by_phandle(display_phandle);
+ if (!ofnode_valid(display_node)) {
+ dev_err(dev, "failed to find display subnode\n");
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
+ if (ret) {
+ dev_err(dev,
+ "required bits-per-pixel property isn't provided\n");
+ return -EINVAL;
+ }
+
+ ret = ofnode_decode_display_timing(display_node, 0, timings);
+ if (ret) {
+ dev_err(dev, "failed to get any display timings\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static int mxs_video_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ struct ctfb_res_modes mode;
+ struct display_timing timings;
+ u32 bpp = 0;
+ u32 fb_start, fb_end;
+ int ret;
+
+ debug("%s() plat: base 0x%lx, size 0x%x\n",
+ __func__, plat->base, plat->size);
+
+ ret = mxs_of_get_timings(dev, &timings, &bpp);
+ if (ret)
+ return ret;
+
+ mode.xres = timings.hactive.typ;
+ mode.yres = timings.vactive.typ;
+ mode.left_margin = timings.hback_porch.typ;
+ mode.right_margin = timings.hfront_porch.typ;
+ mode.upper_margin = timings.vback_porch.typ;
+ mode.lower_margin = timings.vfront_porch.typ;
+ mode.hsync_len = timings.hsync_len.typ;
+ mode.vsync_len = timings.vsync_len.typ;
+ mode.pixclock = HZ2PS(timings.pixelclock.typ);
+
+ ret = mxs_probe_common(&mode, bpp, plat->base);
+ if (ret)
+ return ret;
+
+ switch (bpp) {
+ case 32:
+ case 24:
+ case 18:
+ uc_priv->bpix = VIDEO_BPP32;
+ break;
+ case 16:
+ uc_priv->bpix = VIDEO_BPP16;
+ break;
+ case 8:
+ uc_priv->bpix = VIDEO_BPP8;
+ break;
+ default:
+ dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
+ return -EINVAL;
+ }
+
+ uc_priv->xsize = mode.xres;
+ uc_priv->ysize = mode.yres;
+
+ /* Enable dcache for the frame buffer */
+ fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+ fb_end = plat->base + plat->size;
+ fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+ mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+ DCACHE_WRITEBACK);
+ video_set_flush_dcache(dev, true);
+
+ return ret;
+}
+
+static int mxs_video_bind(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct display_timing timings;
+ u32 bpp = 0;
+ u32 bytes_pp = 0;
+ int ret;
+
+ ret = mxs_of_get_timings(dev, &timings, &bpp);
+ if (ret)
+ return ret;
+
+ switch (bpp) {
+ case 32:
+ case 24:
+ case 18:
+ bytes_pp = 4;
+ break;
+ case 16:
+ bytes_pp = 2;
+ break;
+ case 8:
+ bytes_pp = 1;
+ break;
+ default:
+ dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
+ return -EINVAL;
+ }
+
+ plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
+
+ return 0;
+}
+
+static int mxs_video_remove(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+
+ mxs_remove_common(plat->base);
+
+ return 0;
+}
+
+static const struct udevice_id mxs_video_ids[] = {
+ { .compatible = "fsl,imx23-lcdif" },
+ { .compatible = "fsl,imx28-lcdif" },
+ { .compatible = "fsl,imx7ulp-lcdif" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mxs_video) = {
+ .name = "mxs_video",
+ .id = UCLASS_VIDEO,
+ .of_match = mxs_video_ids,
+ .bind = mxs_video_bind,
+ .probe = mxs_video_probe,
+ .remove = mxs_video_remove,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif /* ifndef CONFIG_DM_VIDEO */
projects / oweals / u-boot.git / blobdiff