Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[oweals/u-boot.git] / drivers / video / ipu_disp.c

diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c
index b4116df8ca1c8e7d771a52c12fc0bed40b160575..948e1fc401facea11502734ac53e82dd70df36e5 100644 (file)
--- a/drivers/video/ipu_disp.c
+++ b/drivers/video/ipu_disp.c
@@ -8,23 +8,7 @@
  *
  * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* #define DEBUG */
@@ -49,7 +33,7 @@ enum csc_type_t {
 
 struct dp_csc_param_t {
        int mode;
-       void *coeff;
+       const int (*coeff)[5][3];
 };
 
 #define SYNC_WAVE 0
@@ -682,13 +666,16 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
        uint32_t csc;
        uint32_t dc_chan = 0;
        int timeout = 50;
+       int irq = 0;
 
        dc_swap = swap;
 
        if (channel == MEM_DC_SYNC) {
                dc_chan = 1;
+               irq = IPU_IRQ_DC_FC_1;
        } else if (channel == MEM_BG_SYNC) {
                dc_chan = 5;
+               irq = IPU_IRQ_DP_SF_END;
        } else if (channel == MEM_FG_SYNC) {
                /* Disable FG channel */
                dc_chan = 5;
@@ -739,25 +726,11 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
                reg ^= DC_WR_CH_CONF_PROG_DI_ID;
                __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
        } else {
-               timeout = 50;
-
-               /* Wait for DC triple buffer to empty */
-               if (g_dc_di_assignment[dc_chan] == 0)
-                       while ((__raw_readl(DC_STAT) & 0x00000002)
-                               != 0x00000002) {
-                               udelay(2000);
-                               timeout -= 2;
-                               if (timeout <= 0)
-                                       break;
-                       }
-               else if (g_dc_di_assignment[dc_chan] == 1)
-                       while ((__raw_readl(DC_STAT) & 0x00000020)
-                               != 0x00000020) {
-                               udelay(2000);
-                               timeout -= 2;
-                               if (timeout <= 0)
-                                       break;
-                       }
+               /* Make sure that we leave at the irq starting edge */
+               __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
+               do {
+                       reg = __raw_readl(IPUIRQ_2_STATREG(irq));
+               } while (!(reg & IPUIRQ_2_MASK(irq)));
 
                reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
                reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
@@ -905,7 +878,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
        debug("panel size = %d x %d\n", width, height);
 
        if ((v_sync_width == 0) || (h_sync_width == 0))
-               return EINVAL;
+               return -EINVAL;
 
        adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
                                         h_start_width, h_end_width,
@@ -1194,7 +1167,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
                if (sig.Vsync_pol)
                        di_gen |= DI_GEN_POLARITY_3;
 
-               if (sig.clk_pol)
+               if (!sig.clk_pol)
                        di_gen |= DI_GEN_POL_CLK;
 
        }