+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* FSL DCU Framebuffer driver
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#define DCU_VSYN_PARA_BP(x) ((x) << 22)
#define DCU_VSYN_PARA_PW(x) ((x) << 11)
#define DCU_VSYN_PARA_FP(x) (x)
-#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6)
+#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
#define DCU_SYN_POL_NEG_REMAIN (0 << 5)
#define DCU_SYN_POL_INV_VS_LOW (1 << 1)
#define DCU_SYN_POL_INV_HS_LOW (1)
/*
* This setting is used for Siliconimage SiI9022A HDMI
*/
-static struct fb_videomode fsl_dcu_mode_640_480 = {
+static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
.name = "640x480-60",
.refresh = 60,
.xres = 640,
.vmode = FB_VMODE_NONINTERLACED,
};
+static struct fb_videomode fsl_dcu_mode_640_480 = {
+ .name = "640x480-60",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 25175,
+ .left_margin = 40,
+ .right_margin = 24,
+ .upper_margin = 32,
+ .lower_margin = 11,
+ .hsync_len = 96,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_800_480 = {
+ .name = "800x480-60",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33260,
+ .left_margin = 216,
+ .right_margin = 40,
+ .upper_margin = 35,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_1024_600 = {
+ .name = "1024x600-60",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 48000,
+ .left_margin = 104,
+ .right_margin = 43,
+ .upper_margin = 24,
+ .lower_margin = 20,
+ .hsync_len = 5,
+ .vsync_len = 5,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
/*
* DCU register map
*/
dcu_write32(®s->ctrldescl[i][9], 0);
dcu_write32(®s->ctrldescl[i][10], 0);
}
-
- dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
}
static int layer_ctrldesc_init(int index, u32 pixel_format)
dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
- dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
-
return 0;
}
memset(info.screen_base, 0, info.screen_size);
reset_total_layers();
- div = dcu_set_pixel_clock(info.var.pixclock);
- dcu_write32(®s->div_ratio, (div - 1));
dcu_write32(®s->disp_size,
DCU_DISP_SIZE_DELTA_Y(info.var.yres) |
DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
dcu_write32(®s->mode,
- DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) |
+ DCU_MODE_BLEND_ITER(2) |
DCU_MODE_RASTER_EN);
dcu_write32(®s->threshold,
layer_ctrldesc_init(0, pixel_format);
+ div = dcu_set_pixel_clock(info.var.pixclock);
+ dcu_write32(®s->div_ratio, (div - 1));
+
+ dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
+
return 0;
}
fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
break;
case RESOLUTION(640, 480):
- fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+ if (!strncmp(options, "monitor=hdmi", 12))
+ fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
+ else
+ fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+ break;
+ case RESOLUTION(800, 480):
+ fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
+ break;
+ case RESOLUTION(1024, 600):
+ fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
break;
default:
printf("unsupported resolution %ux%u\n",