/*-
* Copyright (c) 2007-2008, Juniper Networks, Inc.
* Copyright (c) 2008, Excito Elektronik i Skåne AB
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ *
* All rights reserved.
*
* This program is free software; you can redistribute it and/or
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#define DEBUG
#include <common.h>
#include <asm/byteorder.h>
#include <usb.h>
#include "usb_ehci.h"
int rootdev;
-struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
+struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
volatile struct ehci_hcor *hcor;
static uint16_t portreset;
},
};
-static void ehci_free (void *p, size_t sz)
+#if defined(CONFIG_EHCI_IS_TDI)
+#define ehci_is_TDI() (1)
+#else
+#define ehci_is_TDI() (0)
+#endif
+
+#if defined(CONFIG_EHCI_DCACHE)
+/*
+ * Routines to handle (flush/invalidate) the dcache for the QH and qTD
+ * structures and data buffers. This is needed on platforms using this
+ * EHCI support with dcache enabled.
+ */
+static void flush_invalidate(u32 addr, int size, int flush)
+{
+ if (flush)
+ flush_dcache_range(addr, addr + size);
+ else
+ invalidate_dcache_range(addr, addr + size);
+}
+
+static void cache_qtd(struct qTD *qtd, int flush)
+{
+ u32 *ptr = (u32 *)qtd->qt_buffer[0];
+ int len = (qtd->qt_token & 0x7fff0000) >> 16;
+
+ flush_invalidate((u32)qtd, sizeof(struct qTD), flush);
+ if (ptr && len)
+ flush_invalidate((u32)ptr, len, flush);
+}
+
+
+static inline struct QH *qh_addr(struct QH *qh)
+{
+ return (struct QH *)((u32)qh & 0xffffffe0);
+}
+
+static void cache_qh(struct QH *qh, int flush)
+{
+ struct qTD *qtd;
+ struct qTD *next;
+ static struct qTD *first_qtd;
+
+ /*
+ * Walk the QH list and flush/invalidate all entries
+ */
+ while (1) {
+ flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
+ if ((u32)qh & QH_LINK_TYPE_QH)
+ break;
+ qh = qh_addr(qh);
+ qh = (struct QH *)qh->qh_link;
+ }
+ qh = qh_addr(qh);
+
+ /*
+ * Save first qTD pointer, needed for invalidating pass on this QH
+ */
+ if (flush)
+ first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay &
+ 0xffffffe0);
+ else
+ qtd = first_qtd;
+
+ /*
+ * Walk the qTD list and flush/invalidate all entries
+ */
+ while (1) {
+ if (qtd == NULL)
+ break;
+ cache_qtd(qtd, flush);
+ next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0);
+ if (next == qtd)
+ break;
+ qtd = next;
+ }
+}
+
+static inline void ehci_flush_dcache(struct QH *qh)
+{
+ cache_qh(qh, 1);
+}
+
+static inline void ehci_invalidate_dcache(struct QH *qh)
+{
+ cache_qh(qh, 0);
+}
+#else /* CONFIG_EHCI_DCACHE */
+/*
+ *
+ */
+static inline void ehci_flush_dcache(struct QH *qh)
+{
+}
+
+static inline void ehci_invalidate_dcache(struct QH *qh)
+{
+}
+#endif /* CONFIG_EHCI_DCACHE */
+
+static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
+{
+ uint32_t result;
+ do {
+ result = ehci_readl(ptr);
+ if (result == ~(uint32_t)0)
+ return -1;
+ result &= mask;
+ if (result == done)
+ return 0;
+ udelay(1);
+ usec--;
+ } while (usec > 0);
+ return -1;
+}
+
+static void ehci_free(void *p, size_t sz)
+{
+
+}
+
+static int ehci_reset(void)
{
+ uint32_t cmd;
+ uint32_t tmp;
+ uint32_t *reg_ptr;
+ int ret = 0;
+
+ cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd |= CMD_RESET;
+ ehci_writel(&hcor->or_usbcmd, cmd);
+ ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
+ if (ret < 0) {
+ printf("EHCI fail to reset\n");
+ goto out;
+ }
+
+ if (ehci_is_TDI()) {
+ reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
+ tmp = ehci_readl(reg_ptr);
+ tmp |= USBMODE_CM_HC;
+#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
+ tmp |= USBMODE_BE;
+#endif
+ ehci_writel(reg_ptr, tmp);
+ }
+out:
+ return ret;
}
static void *ehci_alloc(size_t sz, size_t align)
uint32_t endpt, token, usbsts;
uint32_t c, toggle;
uint32_t cmd;
+ int ret = 0;
debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
buffer, length, req);
qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
- usbsts = ehci_readl(hcor->or_usbsts);
- ehci_writel(hcor->or_usbsts, (usbsts & 0x3f));
+ /* Flush dcache */
+ ehci_flush_dcache(&qh_list);
- /* Enable async. schedule. */
- cmd = ehci_readl(hcor->or_usbcmd);
- hcor->or_usbcmd |= CMD_ASE;
- ehci_writel(hcor->or_usbcmd, cmd);
+ usbsts = ehci_readl(&hcor->or_usbsts);
+ ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
- while ((ehci_readl(hcor->or_usbsts) & STD_ASS) == 0)
- udelay(1);
+ /* Enable async. schedule. */
+ cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd |= CMD_ASE;
+ ehci_writel(&hcor->or_usbcmd, cmd);
+
+ ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS,
+ 100 * 1000);
+ if (ret < 0) {
+ printf("EHCI fail timeout STD_ASS set\n");
+ goto fail;
+ }
/* Wait for TDs to be processed. */
ts = get_timer(0);
vtd = td;
do {
+ /* Invalidate dcache */
+ ehci_invalidate_dcache(&qh_list);
token = hc32_to_cpu(vtd->qt_token);
if (!(token & 0x80))
break;
} while (get_timer(ts) < CONFIG_SYS_HZ);
/* Disable async schedule. */
- cmd = ehci_readl(hcor->or_usbcmd);
+ cmd = ehci_readl(&hcor->or_usbcmd);
cmd &= ~CMD_ASE;
- ehci_writel(hcor->or_usbcmd, cmd);
- while ((ehci_readl(hcor->or_usbsts) & STD_ASS) != 0)
- udelay(1);
+ ehci_writel(&hcor->or_usbcmd, cmd);
+
+ ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0,
+ 100 * 1000);
+ if (ret < 0) {
+ printf("EHCI fail timeout STD_ASS reset\n");
+ goto fail;
+ }
qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
} else {
dev->act_len = 0;
debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
- dev->devnum, ehci_readl(hcor->or_usbsts),
- ehci_readl(hcor->or_portsc[0]),
- ehci_readl(hcor->or_portsc[1]));
+ dev->devnum, ehci_readl(&hcor->or_usbsts),
+ ehci_readl(&hcor->or_portsc[0]),
+ ehci_readl(&hcor->or_portsc[1]));
}
return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
void *srcptr = NULL;
int len, srclen;
uint32_t reg;
+ uint32_t *status_reg;
+ if (le16_to_cpu(req->index) >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
+ printf("The request port(%d) is not configured\n",
+ le16_to_cpu(req->index) - 1);
+ return -1;
+ }
+ status_reg = (uint32_t *)&hcor->or_portsc[
+ le16_to_cpu(req->index) - 1];
srclen = 0;
debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
break;
case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
memset(tmpbuf, 0, 4);
- reg = ehci_readl(hcor->or_portsc[le16_to_cpu(req->index)
- - 1]);
+ reg = ehci_readl(status_reg);
if (reg & EHCI_PS_CS)
tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
if (reg & EHCI_PS_PE)
tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
if (reg & EHCI_PS_OCA)
tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
- if (reg & EHCI_PS_PR)
- tmpbuf[0] |= USB_PORT_STAT_RESET;
+ if (reg & EHCI_PS_PR &&
+ (portreset & (1 << le16_to_cpu(req->index)))) {
+ int ret;
+ /* force reset to complete */
+ reg = reg & ~(EHCI_PS_PR | EHCI_PS_CLEAR);
+ ehci_writel(status_reg, reg);
+ ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000);
+ if (!ret)
+ tmpbuf[0] |= USB_PORT_STAT_RESET;
+ else
+ printf("port(%d) reset error\n",
+ le16_to_cpu(req->index) - 1);
+ }
if (reg & EHCI_PS_PP)
tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
- tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
+
+ if (ehci_is_TDI()) {
+ switch ((reg >> 26) & 3) {
+ case 0:
+ break;
+ case 1:
+ tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
+ break;
+ case 2:
+ default:
+ tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
+ break;
+ }
+ } else {
+ tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
+ }
if (reg & EHCI_PS_CSC)
tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
if (portreset & (1 << le16_to_cpu(req->index)))
tmpbuf[2] |= USB_PORT_STAT_C_RESET;
+
srcptr = tmpbuf;
srclen = 4;
break;
case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
- reg = ehci_readl(hcor->or_portsc[le16_to_cpu(req->index) - 1]);
+ reg = ehci_readl(status_reg);
reg &= ~EHCI_PS_CLEAR;
switch (le16_to_cpu(req->value)) {
+ case USB_PORT_FEAT_ENABLE:
+ reg |= EHCI_PS_PE;
+ ehci_writel(status_reg, reg);
+ break;
case USB_PORT_FEAT_POWER:
- reg |= EHCI_PS_PP;
+ if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
+ reg |= EHCI_PS_PP;
+ ehci_writel(status_reg, reg);
+ }
break;
case USB_PORT_FEAT_RESET:
- debug("USB FEAT RESET\n");
- if (EHCI_PS_IS_LOWSPEED(reg)) {
+ if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
+ !ehci_is_TDI() &&
+ EHCI_PS_IS_LOWSPEED(reg)) {
/* Low speed device, give up ownership. */
+ debug("port %d low speed --> companion\n",
+ req->index - 1);
reg |= EHCI_PS_PO;
+ ehci_writel(status_reg, reg);
break;
+ } else {
+ reg |= EHCI_PS_PR;
+ reg &= ~EHCI_PS_PE;
+ ehci_writel(status_reg, reg);
+ /*
+ * caller must wait, then call GetPortStatus
+ * usb 2.0 specification say 50 ms resets on
+ * root
+ */
+ wait_ms(50);
+ portreset |= 1 << le16_to_cpu(req->index);
}
- /* Start reset sequence. */
- reg &= ~EHCI_PS_PE;
- reg |= EHCI_PS_PR;
- ehci_writel(hcor->or_portsc[
- le16_to_cpu(req->index) - 1], reg);
- /* Wait for reset to complete. */
- udelay(500000);
- /* Terminate reset sequence. */
- reg &= ~EHCI_PS_PR;
- /* TODO: is it only fsl chip that requires this
- * manual setting of port enable?
- */
- reg |= EHCI_PS_PE;
- ehci_writel(hcor->or_portsc[
- le16_to_cpu(req->index) - 1], reg);
- /* Wait for HC to complete reset. */
- udelay(2000);
- reg =
- ehci_readl(hcor->or_portsc[le16_to_cpu(req->index)
- - 1]);
- reg &= ~EHCI_PS_CLEAR;
- if ((reg & EHCI_PS_PE) == 0) {
- /* Not a high speed device, give up
- * ownership. */
- reg |= EHCI_PS_PO;
- break;
- }
- portreset |= 1 << le16_to_cpu(req->index);
break;
default:
debug("unknown feature %x\n", le16_to_cpu(req->value));
goto unknown;
}
- ehci_writel(hcor->or_portsc[le16_to_cpu(req->index) - 1], reg);
+ /* unblock posted writes */
+ ehci_readl(&hcor->or_usbcmd);
break;
case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
- reg = ehci_readl(hcor->or_portsc[le16_to_cpu(req->index) - 1]);
- reg &= ~EHCI_PS_CLEAR;
+ reg = ehci_readl(status_reg);
switch (le16_to_cpu(req->value)) {
case USB_PORT_FEAT_ENABLE:
reg &= ~EHCI_PS_PE;
break;
+ case USB_PORT_FEAT_C_ENABLE:
+ reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
+ break;
+ case USB_PORT_FEAT_POWER:
+ if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
+ reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
case USB_PORT_FEAT_C_CONNECTION:
- reg |= EHCI_PS_CSC;
+ reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
+ break;
+ case USB_PORT_FEAT_OVER_CURRENT:
+ reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
break;
case USB_PORT_FEAT_C_RESET:
portreset &= ~(1 << le16_to_cpu(req->index));
debug("unknown feature %x\n", le16_to_cpu(req->value));
goto unknown;
}
- ehci_writel(hcor->or_portsc[le16_to_cpu(req->index) - 1], reg);
+ ehci_writel(status_reg, reg);
+ /* unblock posted write */
+ ehci_readl(&hcor->or_usbcmd);
break;
default:
debug("Unknown request\n");
if (ehci_hcd_init() != 0)
return -1;
+ /* EHCI spec section 4.1 */
+ if (ehci_reset() != 0)
+ return -1;
+
+#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
+ if (ehci_hcd_init() != 0)
+ return -1;
+#endif
+
/* Set head of reclaim list */
memset(&qh_list, 0, sizeof(qh_list));
qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
/* Set async. queue head pointer. */
- ehci_writel(hcor->or_asynclistaddr, (uint32_t)&qh_list);
+ ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
- reg = ehci_readl(hccr->cr_hcsparams);
- descriptor.hub.bNbrPorts = reg & 0xf;
- printf("NbrPorts %x\n", descriptor.hub.bNbrPorts);
- if (reg & 0x10000) /* Port Indicators */
+ reg = ehci_readl(&hccr->cr_hcsparams);
+ descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
+ printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
+ /* Port Indicators */
+ if (HCS_INDICATOR(reg))
descriptor.hub.wHubCharacteristics |= 0x80;
- if (reg & 0x10) /* Port Power Control */
+ /* Port Power Control */
+ if (HCS_PPC(reg))
descriptor.hub.wHubCharacteristics |= 0x01;
- /* take control over the ports */
- cmd = ehci_readl(hcor->or_configflag);
- cmd |= 1;
- ehci_writel(hcor->or_configflag, cmd);
-
/* Start the host controller. */
- cmd = ehci_readl(hcor->or_configflag);
- cmd |= 1;
- ehci_writel(hcor->or_usbcmd, cmd);
+ cmd = ehci_readl(&hcor->or_usbcmd);
+ /* Philips, Intel, and maybe others need CMD_RUN before the
+ * root hub will detect new devices (why?); NEC doesn't */
+ cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
+ cmd |= CMD_RUN;
+ ehci_writel(&hcor->or_usbcmd, cmd);
+
+ /* take control over the ports */
+ cmd = ehci_readl(&hcor->or_configflag);
+ cmd |= FLAG_CF;
+ ehci_writel(&hcor->or_configflag, cmd);
+ /* unblock posted write */
+ cmd = ehci_readl(&hcor->or_usbcmd);
+ wait_ms(5);
+ reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
+ printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
rootdev = 0;
projects / oweals / u-boot.git / blobdiff