+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2016 Rockchip, Inc.
* Authors: Daniel Meng <daniel.meng@rock-chips.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
-#include <fdtdec.h>
-#include <libfdt.h>
#include <malloc.h>
#include <usb.h>
#include <watchdog.h>
#include "xhci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct rockchip_xhci_platdata {
fdt_addr_t hcd_base;
- fdt_addr_t phy_base;
struct udevice *vbus_supply;
};
static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
{
struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
- struct udevice *child;
int ret = 0;
/*
* Get the base address for XHCI controller from the device node
*/
- plat->hcd_base = devfdt_get_addr(dev);
+ plat->hcd_base = dev_read_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
- debug("Can't get the XHCI register base address\n");
- return -ENXIO;
- }
-
- /* Get the base address for usbphy from the device node */
- for (device_find_first_child(dev, &child); child;
- device_find_next_child(&child)) {
- if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy"))
- continue;
- plat->phy_base = devfdt_get_addr(child);
- break;
- }
-
- if (plat->phy_base == FDT_ADDR_T_NONE) {
- debug("Can't get the usbphy register address\n");
+ pr_err("Can't get the XHCI register base address\n");
return -ENXIO;
}
-#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
/* Vbus regulator */
ret = device_get_supply_regulator(dev, "vbus-supply",
&plat->vbus_supply);
if (ret)
- debug("Can't get vbus supply\n");
-#endif
+ debug("Can't get VBus regulator!\n");
return 0;
}
struct udevice *dev)
{
u32 reg;
- const void *blob = gd->fdt_blob;
u32 utmi_bits;
/* Set dwc3 usb2 phy config */
reg = readl(&dwc3_reg->g_usb2phycfg[0]);
- if (fdtdec_get_bool(blob, dev_of_offset(dev),
- "snps,dis-enblslpm-quirk"))
+ if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
- utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev),
- "snps,phyif-utmi-bits", -1);
+ utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
if (utmi_bits == 16) {
reg |= DWC3_GUSB2PHYCFG_PHYIF;
reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
}
- if (fdtdec_get_bool(blob, dev_of_offset(dev),
- "snps,dis-u2-freeclk-exists-quirk"))
+ if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
- if (fdtdec_get_bool(blob, dev_of_offset(dev),
- "snps,dis-u2-susphy-quirk"))
+ if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
writel(reg, &dwc3_reg->g_usb2phycfg[0]);
ret = dwc3_core_init(rkxhci->dwc3_reg);
if (ret) {
- debug("failed to initialize core\n");
+ pr_err("failed to initialize core\n");
return ret;
}
hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
-#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
- ret = regulator_set_enable(plat->vbus_supply, true);
- if (ret)
- debug("XHCI: Failed to enable vbus supply\n");
-#endif
+ if (plat->vbus_supply) {
+ ret = regulator_set_enable(plat->vbus_supply, true);
+ if (ret) {
+ pr_err("XHCI: failed to set VBus supply\n");
+ return ret;
+ }
+ }
ret = rockchip_xhci_core_init(ctx, dev);
if (ret) {
- debug("XHCI: failed to initialize controller\n");
+ pr_err("XHCI: failed to initialize controller\n");
return ret;
}
if (ret)
return ret;
-#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
- ret = regulator_set_enable(plat->vbus_supply, false);
- if (ret)
- debug("XHCI: Failed to disable vbus supply\n");
-#endif
+ if (plat->vbus_supply) {
+ ret = regulator_set_enable(plat->vbus_supply, false);
+ if (ret)
+ pr_err("XHCI: failed to set VBus supply\n");
+ }
- return 0;
+ return ret;
}
static const struct udevice_id xhci_usb_ids[] = {