#include <common.h>
#include <dm.h>
+#include <fdtdec.h>
+#include <generic-phy.h>
#include <usb.h>
#include "xhci.h"
#include <asm/io.h>
#include <linux/usb/dwc3.h>
+#include <linux/usb/otg.h>
DECLARE_GLOBAL_DATA_PTR;
+struct xhci_dwc3_platdata {
+ struct phy usb_phy;
+};
+
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
GFLADJ_30MHZ(val));
}
+#ifdef CONFIG_DM_USB
static int xhci_dwc3_probe(struct udevice *dev)
{
struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
struct xhci_hcor *hcor;
struct xhci_hccr *hccr;
struct dwc3 *dwc3_reg;
+ enum usb_dr_mode dr_mode;
+ int ret;
- hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
- hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
+ hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
+ hcor = (struct xhci_hcor *)((uintptr_t)hccr +
HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+ ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
+ if (ret) {
+ if (ret != -ENOENT) {
+ pr_err("Failed to get USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ } else {
+ ret = generic_phy_init(&plat->usb_phy);
+ if (ret) {
+ pr_err("Can't init USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ }
+
dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
dwc3_core_init(dwc3_reg);
+ dr_mode = usb_get_dr_mode(dev_of_offset(dev));
+ if (dr_mode == USB_DR_MODE_UNKNOWN)
+ /* by default set dual role mode to HOST */
+ dr_mode = USB_DR_MODE_HOST;
+
+ dwc3_set_mode(dwc3_reg, dr_mode);
+
return xhci_register(dev, hccr, hcor);
}
static int xhci_dwc3_remove(struct udevice *dev)
{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ if (generic_phy_valid(&plat->usb_phy)) {
+ ret = generic_phy_exit(&plat->usb_phy);
+ if (ret) {
+ pr_err("Can't deinit USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ }
+
return xhci_deregister(dev);
}
.platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
+#endif