#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/mx6x_pins.h>
-#include <asm/arch/iomux-v3.h>
+#include <asm/imx-common/iomux-v3.h>
#include "ehci.h"
-#include "ehci-core.h"
#define USB_OTGREGS_OFFSET 0x000
#define USB_H1REGS_OFFSET 0x200
#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
-#define ANADIG_USB2_CHRG_DETECT 0x00000210
#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
-#define ANADIG_USB2_PLL_480_CTRL 0x00000020
-#define ANADIG_USB2_PLL_480_CTRL_SET 0x00000024
-#define ANADIG_USB2_PLL_480_CTRL_CLR 0x00000028
#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
static void usbh1_power_config(void)
{
- void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR;
-
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
/*
* Some phy and power's special controls for host1
* 1. The external charger detector needs to be disabled
*/
__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
- anatop_base + ANADIG_USB2_CHRG_DETECT);
+ &anatop->usb2_chrg_detect);
__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
- anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR);
+ &anatop->usb2_pll_480_ctrl_clr);
__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
ANADIG_USB2_PLL_480_CTRL_POWER |
ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
- anatop_base + ANADIG_USB2_PLL_480_CTRL_SET);
+ &anatop->usb2_pll_480_ctrl_set);
}
static int usbh1_phy_enable(void)
__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
}
-int ehci_hcd_init(void)
+int __weak board_ehci_hcd_init(int port)
+{
+ return 0;
+}
+
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
(0x200 * CONFIG_MXC_USB_PORT));
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}