#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/iomux-v3.h>
+#include <dm.h>
#include "ehci.h"
#define USBNC_OFFSET 0x200
#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
-#define UCTRL_PM (1 << 9) /* OTG Power Mask */
+#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
(0x10000 * index) + USBNC_OFFSET);
void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
+ void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
/*
* Clear the ACAENB to enable usb_otg_id detection,
* otherwise it is the ACA detection enabled.
*/
clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+
+ /* Set power polarity to high active */
+#ifdef CONFIG_MXC_USB_OTG_HACTIVE
+ setbits_le32(ctrl, UCTRL_PWR_POL);
+#else
+ clrbits_le32(ctrl, UCTRL_PWR_POL);
+#endif
}
int usb_phy_mode(int port)
setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#endif
-#if defined(CONFIG_MX6)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
-#elif defined(CONFIG_MX7)
- setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
-#endif
}
/**
return 0;
}
+int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
+{
+ int ret;
+
+ enable_usboh3_clk(1);
+ mdelay(1);
+
+ /* Do board specific initialization */
+ ret = board_ehci_hcd_init(index);
+ if (ret)
+ return ret;
+
+ usb_power_config(index);
+ usb_oc_config(index);
+
+#if defined(CONFIG_MX6)
+ usb_internal_phy_clock_gate(index, 1);
+ usb_phy_enable(index, ehci);
+#endif
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_USB
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
if (index > 3)
return -EINVAL;
- enable_usboh3_clk(1);
- mdelay(1);
- /* Do board specific initialization */
- ret = board_ehci_hcd_init(index);
+ ret = ehci_mx6_common_init(ehci, index);
if (ret)
return ret;
- usb_power_config(index);
- usb_oc_config(index);
-
-#if defined(CONFIG_MX6)
- usb_internal_phy_clock_gate(index, 1);
- usb_phy_enable(index, ehci);
-#endif
type = board_usb_phy_mode(index);
- *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
- HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ if (hccr && hcor) {
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ }
if ((type == init) || (type == USB_INIT_DEVICE))
board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
{
return 0;
}
+#else
+struct ehci_mx6_priv_data {
+ struct ehci_ctrl ctrl;
+ struct usb_ehci *ehci;
+ enum usb_init_type init_type;
+ int portnr;
+};
+
+static int mx6_init_after_reset(struct ehci_ctrl *dev)
+{
+ struct ehci_mx6_priv_data *priv = dev->priv;
+ enum usb_init_type type = priv->init_type;
+ struct usb_ehci *ehci = priv->ehci;
+ int ret;
+
+ ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
+ if (ret)
+ return ret;
+
+ board_ehci_power(priv->portnr, (type == USB_INIT_DEVICE) ? 0 : 1);
+
+ if (type == USB_INIT_DEVICE)
+ return 0;
+
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+
+ mdelay(10);
+
+ return 0;
+}
+
+static const struct ehci_ops mx6_ehci_ops = {
+ .init_after_reset = mx6_init_after_reset
+};
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev);
+ struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ int ret;
+
+ priv->ehci = ehci;
+ priv->portnr = dev->seq;
+ priv->init_type = plat->init_type;
+
+ ret = ehci_mx6_common_init(ehci, priv->portnr);
+ if (ret)
+ return ret;
+
+ board_ehci_power(priv->portnr, (priv->init_type == USB_INIT_DEVICE) ? 0 : 1);
+
+ if (priv->init_type == USB_INIT_HOST) {
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+ }
+
+ mdelay(10);
+
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ hcor = (struct ehci_hcor *)((uint32_t)hccr +
+ HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
+
+ return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
+}
+
+static int ehci_usb_remove(struct udevice *dev)
+{
+ int ret;
+
+ ret = ehci_deregister(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id mx6_usb_ids[] = {
+ { .compatible = "fsl,imx27-usb" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_mx6) = {
+ .name = "ehci_mx6",
+ .id = UCLASS_USB,
+ .of_match = mx6_usb_ids,
+ .probe = ehci_usb_probe,
+ .remove = ehci_usb_remove,
+ .ops = &ehci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
projects / oweals / u-boot.git / blobdiff