ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULP

[oweals/u-boot.git] / drivers / usb / host / ehci-mx6.c

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index e9e6ed596d599100124e8af90a24ca5a3c823efe..1993ad620a8cc3b573f9d3e4a2e3d5b4d7ab1ad1 100644 (file)
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -64,10 +64,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
 #define UCMD_RESET             (1 << 1) /* controller reset */
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
 static const unsigned phy_bases[] = {
        USB_PHY0_BASE_ADDR,
+#if defined(USB_PHY1_BASE_ADDR)
        USB_PHY1_BASE_ADDR,
+#endif
 };
 
 static void usb_internal_phy_clock_gate(int index, int on)
@@ -84,6 +86,20 @@ static void usb_internal_phy_clock_gate(int index, int on)
 
 static void usb_power_config(int index)
 {
+#if defined(CONFIG_MX7ULP)
+       struct usbphy_regs __iomem *usbphy =
+               (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
+
+       if (index > 0)
+               return;
+
+       writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+                  ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
+                  &usbphy->usb1_chrg_detect);
+
+       scg_enable_usb_pll(true);
+
+#else
        struct anatop_regs __iomem *anatop =
                (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
        void __iomem *chrg_detect;
@@ -123,6 +139,8 @@ static void usb_power_config(int index)
                     ANADIG_USB2_PLL_480_CTRL_POWER |
                     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
                     pll_480_ctrl_set);
+
+#endif
 }
 
 /* Return 0 : host node, <>0 : device mode */
@@ -185,6 +203,14 @@ int usb_phy_mode(int port)
                return USB_INIT_HOST;
 }
 
+#if defined(CONFIG_MX7ULP)
+struct usbnc_regs {
+       u32 ctrl1;
+       u32 ctrl2;
+       u32 reserve0[2];
+       u32 hsic_ctrl;
+};
+#else
 /* Base address for this IP block is 0x02184800 */
 struct usbnc_regs {
        u32     ctrl[4];        /* otg/host1-3 */
@@ -193,6 +219,8 @@ struct usbnc_regs {
        u32     otg_phy_ctrl_0;
        u32     uh1_phy_ctrl_0;
 };
+#endif
+
 #elif defined(CONFIG_MX7)
 struct usbnc_regs {
        u32 ctrl1;
@@ -213,20 +241,12 @@ static void usb_power_config(int index)
        struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
                        (0x10000 * index) + USBNC_OFFSET);
        void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
-       void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
 
        /*
         * Clear the ACAENB to enable usb_otg_id detection,
         * otherwise it is the ACA detection enabled.
         */
        clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
-
-       /* Set power polarity to high active */
-#ifdef CONFIG_MXC_USB_OTG_HACTIVE
-       setbits_le32(ctrl, UCTRL_PWR_POL);
-#else
-       clrbits_le32(ctrl, UCTRL_PWR_POL);
-#endif
 }
 
 int usb_phy_mode(int port)
@@ -251,7 +271,7 @@ static void usb_oc_config(int index)
        struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
                        USB_OTHERREGS_OFFSET);
        void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
-#elif defined(CONFIG_MX7)
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
        struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
                        (0x10000 * index) + USBNC_OFFSET);
        void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
@@ -265,6 +285,13 @@ static void usb_oc_config(int index)
 #endif
 
        setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
+
+       /* Set power polarity to high active */
+#ifdef CONFIG_MXC_USB_OTG_HACTIVE
+       setbits_le32(ctrl, UCTRL_PWR_POL);
+#else
+       clrbits_le32(ctrl, UCTRL_PWR_POL);
+#endif
 }
 
 /**
@@ -328,7 +355,7 @@ int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
        usb_power_config(index);
        usb_oc_config(index);
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
        usb_internal_phy_clock_gate(index, 1);
        usb_phy_enable(index, ehci);
 #endif
@@ -343,7 +370,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
        enum usb_init_type type;
 #if defined(CONFIG_MX6)
        u32 controller_spacing = 0x200;
-#elif defined(CONFIG_MX7)
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
        u32 controller_spacing = 0x10000;
 #endif
        struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
@@ -446,7 +473,7 @@ static int ehci_usb_phy_mode(struct udevice *dev)
         * About fsl,usbphy, Refer to
         * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
         */
-       if (is_mx6()) {
+       if (is_mx6() || is_mx7ulp()) {
                phy_off = fdtdec_lookup_phandle(blob,
                                                offset,
                                                "fsl,usbphy");
@@ -513,10 +540,11 @@ static int ehci_usb_bind(struct udevice *dev)
         * from which it derives offsets in the PHY and ANATOP register sets.
         *
         * Here we attempt to calculate these indexes from DT information as
-        * well as we can. The USB controllers on all existing iMX6/iMX7 SoCs
-        * are placed next to each other, at addresses incremented by 0x200.
-        * Thus, the index is derived from the multiple of 0x200 offset from
-        * the first controller address.
+        * well as we can. The USB controllers on all existing iMX6 SoCs
+        * are placed next to each other, at addresses incremented by 0x200,
+        * and iMX7 their addresses are shifted by 0x10000.
+        * Thus, the index is derived from the multiple of 0x200 (0x10000 for
+        * iMX7) offset from the first controller address.
         *
         * However, to complete conversion of this driver to DT probing, the
         * following has to be done:
@@ -531,10 +559,10 @@ static int ehci_usb_bind(struct udevice *dev)
         * With these changes in place, the ad-hoc indexing goes away and
         * the driver is fully converted to DT probing.
         */
-       fdt_size_t size;
-       fdt_addr_t addr = devfdt_get_addr_size_index(dev, 0, &size);
+       u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
+       fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
 
-       dev->req_seq = (addr - USB_BASE_ADDR) / size;
+       dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
 
        return 0;
 }