#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
+#if defined(USB_PHY1_BASE_ADDR)
USB_PHY1_BASE_ADDR,
+#endif
};
static void usb_internal_phy_clock_gate(int index, int on)
static void usb_power_config(int index)
{
+#if defined(CONFIG_MX7ULP)
+ struct usbphy_regs __iomem *usbphy =
+ (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
+
+ if (index > 0)
+ return;
+
+ writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+ ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
+ &usbphy->usb1_chrg_detect);
+
+ scg_enable_usb_pll(true);
+
+#else
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
void __iomem *chrg_detect;
ANADIG_USB2_PLL_480_CTRL_POWER |
ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
pll_480_ctrl_set);
+
+#endif
}
/* Return 0 : host node, <>0 : device mode */
return USB_INIT_HOST;
}
+#if defined(CONFIG_MX7ULP)
+struct usbnc_regs {
+ u32 ctrl1;
+ u32 ctrl2;
+ u32 reserve0[2];
+ u32 hsic_ctrl;
+};
+#else
/* Base address for this IP block is 0x02184800 */
struct usbnc_regs {
u32 ctrl[4]; /* otg/host1-3 */
u32 otg_phy_ctrl_0;
u32 uh1_phy_ctrl_0;
};
+#endif
+
#elif defined(CONFIG_MX7)
struct usbnc_regs {
u32 ctrl1;
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
(0x10000 * index) + USBNC_OFFSET);
void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
- void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
/*
* Clear the ACAENB to enable usb_otg_id detection,
* otherwise it is the ACA detection enabled.
*/
clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
-
- /* Set power polarity to high active */
-#ifdef CONFIG_MXC_USB_OTG_HACTIVE
- setbits_le32(ctrl, UCTRL_PWR_POL);
-#else
- clrbits_le32(ctrl, UCTRL_PWR_POL);
-#endif
}
int usb_phy_mode(int port)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
USB_OTHERREGS_OFFSET);
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
-#elif defined(CONFIG_MX7)
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
(0x10000 * index) + USBNC_OFFSET);
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
#endif
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
+
+ /* Set power polarity to high active */
+#ifdef CONFIG_MXC_USB_OTG_HACTIVE
+ setbits_le32(ctrl, UCTRL_PWR_POL);
+#else
+ clrbits_le32(ctrl, UCTRL_PWR_POL);
+#endif
}
/**
usb_power_config(index);
usb_oc_config(index);
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(index, 1);
usb_phy_enable(index, ehci);
#endif
enum usb_init_type type;
#if defined(CONFIG_MX6)
u32 controller_spacing = 0x200;
-#elif defined(CONFIG_MX7)
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
u32 controller_spacing = 0x10000;
#endif
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
* About fsl,usbphy, Refer to
* Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
*/
- if (is_mx6()) {
+ if (is_mx6() || is_mx7ulp()) {
phy_off = fdtdec_lookup_phandle(blob,
offset,
"fsl,usbphy");
return 0;
}
+static int ehci_usb_bind(struct udevice *dev)
+{
+ /*
+ * TODO:
+ * This driver is only partly converted to DT probing and still uses
+ * a tremendous amount of hard-coded addresses. To make things worse,
+ * the driver depends on specific sequential indexing of controllers,
+ * from which it derives offsets in the PHY and ANATOP register sets.
+ *
+ * Here we attempt to calculate these indexes from DT information as
+ * well as we can. The USB controllers on all existing iMX6 SoCs
+ * are placed next to each other, at addresses incremented by 0x200,
+ * and iMX7 their addresses are shifted by 0x10000.
+ * Thus, the index is derived from the multiple of 0x200 (0x10000 for
+ * iMX7) offset from the first controller address.
+ *
+ * However, to complete conversion of this driver to DT probing, the
+ * following has to be done:
+ * - DM clock framework support for iMX must be implemented
+ * - usb_power_config() has to be converted to clock framework
+ * -> Thus, the ad-hoc "index" variable goes away.
+ * - USB PHY handling has to be factored out into separate driver
+ * -> Thus, the ad-hoc "index" variable goes away from the PHY
+ * code, the PHY driver must parse it's address from DT. This
+ * USB driver must find the PHY driver via DT phandle.
+ * -> usb_power_config() shall be moved to PHY driver
+ * With these changes in place, the ad-hoc indexing goes away and
+ * the driver is fully converted to DT probing.
+ */
+ u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
+ fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
+
+ dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
+
+ return 0;
+}
+
static int ehci_usb_probe(struct udevice *dev)
{
struct usb_platdata *plat = dev_get_platdata(dev);
.id = UCLASS_USB,
.of_match = mx6_usb_ids,
.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .bind = ehci_usb_bind,
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
projects / oweals / u-boot.git / blobdiff