+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <usb.h>
#include <errno.h>
+#include <wait_bit.h>
#include <linux/compiler.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <dm.h>
+#include <asm/mach-types.h>
+#include <power/regulator.h>
+#include <linux/usb/otg.h>
#include "ehci.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define USB_OTGREGS_OFFSET 0x000
#define USB_H1REGS_OFFSET 0x200
#define USB_H2REGS_OFFSET 0x400
#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
-
+#define USBNC_OFFSET 0x200
+#define USBNC_PHY_STATUS_OFFSET 0x23C
+#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
+#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
+#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
+#if defined(USB_PHY1_BASE_ADDR)
USB_PHY1_BASE_ADDR,
+#endif
};
static void usb_internal_phy_clock_gate(int index, int on)
static void usb_power_config(int index)
{
+#if defined(CONFIG_MX7ULP)
+ struct usbphy_regs __iomem *usbphy =
+ (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
+
+ if (index > 0)
+ return;
+
+ writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+ ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
+ &usbphy->usb1_chrg_detect);
+
+ scg_enable_usb_pll(true);
+
+#else
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
void __iomem *chrg_detect;
ANADIG_USB2_PLL_480_CTRL_POWER |
ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
pll_480_ctrl_set);
+
+#endif
}
/* Return 0 : host node, <>0 : device mode */
void __iomem *phy_reg;
void __iomem *phy_ctrl;
void __iomem *usb_cmd;
+ int ret;
if (index >= ARRAY_SIZE(phy_bases))
return 0;
/* Stop then Reset */
clrbits_le32(usb_cmd, UCMD_RUN_STOP);
- while (readl(usb_cmd) & UCMD_RUN_STOP)
- ;
+ ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
+ if (ret)
+ return ret;
setbits_le32(usb_cmd, UCMD_RESET);
- while (readl(usb_cmd) & UCMD_RESET)
- ;
+ ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
+ if (ret)
+ return ret;
/* Reset USBPHY module */
setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
return 0;
}
+int usb_phy_mode(int port)
+{
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
+ u32 val;
+
+ phy_reg = (void __iomem *)phy_bases[port];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+ val = readl(phy_ctrl);
+
+ if (val & USBPHY_CTRL_OTG_ID)
+ return USB_INIT_DEVICE;
+ else
+ return USB_INIT_HOST;
+}
+
+#if defined(CONFIG_MX7ULP)
+struct usbnc_regs {
+ u32 ctrl1;
+ u32 ctrl2;
+ u32 reserve0[2];
+ u32 hsic_ctrl;
+};
+#else
/* Base address for this IP block is 0x02184800 */
struct usbnc_regs {
u32 ctrl[4]; /* otg/host1-3 */
u32 otg_phy_ctrl_0;
u32 uh1_phy_ctrl_0;
};
+#endif
+
+#elif defined(CONFIG_MX7)
+struct usbnc_regs {
+ u32 ctrl1;
+ u32 ctrl2;
+ u32 reserve1[10];
+ u32 phy_cfg1;
+ u32 phy_cfg2;
+ u32 reserve2;
+ u32 phy_status;
+ u32 reserve3[4];
+ u32 adp_cfg1;
+ u32 adp_cfg2;
+ u32 adp_status;
+};
+
+static void usb_power_config(int index)
+{
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x10000 * index) + USBNC_OFFSET);
+ void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
+
+ /*
+ * Clear the ACAENB to enable usb_otg_id detection,
+ * otherwise it is the ACA detection enabled.
+ */
+ clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+}
+
+int usb_phy_mode(int port)
+{
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x10000 * port) + USBNC_OFFSET);
+ void __iomem *status = (void __iomem *)(&usbnc->phy_status);
+ u32 val;
+
+ val = readl(status);
+
+ if (val & USBNC_PHYSTATUS_ID_DIG)
+ return USB_INIT_DEVICE;
+ else
+ return USB_INIT_HOST;
+}
+#endif
static void usb_oc_config(int index)
{
+#if defined(CONFIG_MX6)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
USB_OTHERREGS_OFFSET);
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x10000 * index) + USBNC_OFFSET);
+ void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
+#endif
#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
/* mx6qarm2 seems to required a different setting*/
#endif
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
-}
-
-int usb_phy_mode(int port)
-{
- void __iomem *phy_reg;
- void __iomem *phy_ctrl;
- u32 val;
-
- phy_reg = (void __iomem *)phy_bases[port];
- phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
- val = readl(phy_ctrl);
-
- if (val & USBPHY_CTRL_OTG_ID)
- return USB_INIT_DEVICE;
- else
- return USB_INIT_HOST;
+ /* Set power polarity to high active */
+#ifdef CONFIG_MXC_USB_OTG_HACTIVE
+ setbits_le32(ctrl, UCTRL_PWR_POL);
+#else
+ clrbits_le32(ctrl, UCTRL_PWR_POL);
+#endif
}
/**
- * board_ehci_hcd_init - override usb phy mode
+ * board_usb_phy_mode - override usb phy mode
* @port: usb host/otg port
*
* Target board specific, override usb_phy_mode.
return 0;
}
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
{
- enum usb_init_type type;
- struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
- (0x200 * index));
+ int ret;
- if (index > 3)
- return -EINVAL;
enable_usboh3_clk(1);
mdelay(1);
/* Do board specific initialization */
- board_ehci_hcd_init(index);
+ ret = board_ehci_hcd_init(index);
+ if (ret)
+ return ret;
usb_power_config(index);
usb_oc_config(index);
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(index, 1);
usb_phy_enable(index, ehci);
+#endif
+
+ return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_USB)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ enum usb_init_type type;
+#if defined(CONFIG_MX6)
+ u32 controller_spacing = 0x200;
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
+ u32 controller_spacing = 0x10000;
+#endif
+ struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
+ (controller_spacing * index));
+ int ret;
+
+ if (index > 3)
+ return -EINVAL;
+
+ ret = ehci_mx6_common_init(ehci, index);
+ if (ret)
+ return ret;
+
type = board_usb_phy_mode(index);
- *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
- HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ if (hccr && hcor) {
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ }
if ((type == init) || (type == USB_INIT_DEVICE))
board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
return -ENODEV;
if (type == USB_INIT_DEVICE)
return 0;
+
setbits_le32(&ehci->usbmode, CM_HOST);
writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
{
return 0;
}
+#else
+struct ehci_mx6_priv_data {
+ struct ehci_ctrl ctrl;
+ struct usb_ehci *ehci;
+ struct udevice *vbus_supply;
+ enum usb_init_type init_type;
+ int portnr;
+};
+
+static int mx6_init_after_reset(struct ehci_ctrl *dev)
+{
+ struct ehci_mx6_priv_data *priv = dev->priv;
+ enum usb_init_type type = priv->init_type;
+ struct usb_ehci *ehci = priv->ehci;
+ int ret;
+
+ ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->vbus_supply) {
+ ret = regulator_set_enable(priv->vbus_supply,
+ (type == USB_INIT_DEVICE) ?
+ false : true);
+ if (ret) {
+ puts("Error enabling VBUS supply\n");
+ return ret;
+ }
+ }
+#endif
+
+ if (type == USB_INIT_DEVICE)
+ return 0;
+
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+
+ mdelay(10);
+
+ return 0;
+}
+
+static const struct ehci_ops mx6_ehci_ops = {
+ .init_after_reset = mx6_init_after_reset
+};
+
+static int ehci_usb_phy_mode(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
+ void *__iomem phy_ctrl, *__iomem phy_status;
+ const void *blob = gd->fdt_blob;
+ int offset = dev_of_offset(dev), phy_off;
+ u32 val;
+
+ /*
+ * About fsl,usbphy, Refer to
+ * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
+ */
+ if (is_mx6() || is_mx7ulp()) {
+ phy_off = fdtdec_lookup_phandle(blob,
+ offset,
+ "fsl,usbphy");
+ if (phy_off < 0)
+ return -EINVAL;
+
+ addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
+ "reg");
+ if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
+ val = readl(phy_ctrl);
+
+ if (val & USBPHY_CTRL_OTG_ID)
+ plat->init_type = USB_INIT_DEVICE;
+ else
+ plat->init_type = USB_INIT_HOST;
+ } else if (is_mx7()) {
+ phy_status = (void __iomem *)(addr +
+ USBNC_PHY_STATUS_OFFSET);
+ val = readl(phy_status);
+
+ if (val & USBNC_PHYSTATUS_ID_DIG)
+ plat->init_type = USB_INIT_DEVICE;
+ else
+ plat->init_type = USB_INIT_HOST;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ enum usb_dr_mode dr_mode;
+
+ dr_mode = usb_get_dr_mode(dev_of_offset(dev));
+
+ switch (dr_mode) {
+ case USB_DR_MODE_HOST:
+ plat->init_type = USB_INIT_HOST;
+ break;
+ case USB_DR_MODE_PERIPHERAL:
+ plat->init_type = USB_INIT_DEVICE;
+ break;
+ case USB_DR_MODE_OTG:
+ case USB_DR_MODE_UNKNOWN:
+ return ehci_usb_phy_mode(dev);
+ };
+
+ return 0;
+}
+
+static int ehci_usb_bind(struct udevice *dev)
+{
+ /*
+ * TODO:
+ * This driver is only partly converted to DT probing and still uses
+ * a tremendous amount of hard-coded addresses. To make things worse,
+ * the driver depends on specific sequential indexing of controllers,
+ * from which it derives offsets in the PHY and ANATOP register sets.
+ *
+ * Here we attempt to calculate these indexes from DT information as
+ * well as we can. The USB controllers on all existing iMX6 SoCs
+ * are placed next to each other, at addresses incremented by 0x200,
+ * and iMX7 their addresses are shifted by 0x10000.
+ * Thus, the index is derived from the multiple of 0x200 (0x10000 for
+ * iMX7) offset from the first controller address.
+ *
+ * However, to complete conversion of this driver to DT probing, the
+ * following has to be done:
+ * - DM clock framework support for iMX must be implemented
+ * - usb_power_config() has to be converted to clock framework
+ * -> Thus, the ad-hoc "index" variable goes away.
+ * - USB PHY handling has to be factored out into separate driver
+ * -> Thus, the ad-hoc "index" variable goes away from the PHY
+ * code, the PHY driver must parse it's address from DT. This
+ * USB driver must find the PHY driver via DT phandle.
+ * -> usb_power_config() shall be moved to PHY driver
+ * With these changes in place, the ad-hoc indexing goes away and
+ * the driver is fully converted to DT probing.
+ */
+ u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
+ fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
+
+ dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
+
+ return 0;
+}
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
+ struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
+ enum usb_init_type type = plat->init_type;
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ int ret;
+
+ priv->ehci = ehci;
+ priv->portnr = dev->seq;
+ priv->init_type = type;
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ ret = device_get_supply_regulator(dev, "vbus-supply",
+ &priv->vbus_supply);
+ if (ret)
+ debug("%s: No vbus supply\n", dev->name);
+#endif
+ ret = ehci_mx6_common_init(ehci, priv->portnr);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->vbus_supply) {
+ ret = regulator_set_enable(priv->vbus_supply,
+ (type == USB_INIT_DEVICE) ?
+ false : true);
+ if (ret) {
+ puts("Error enabling VBUS supply\n");
+ return ret;
+ }
+ }
+#endif
+
+ if (priv->init_type == USB_INIT_HOST) {
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+ }
+
+ mdelay(10);
+
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ hcor = (struct ehci_hcor *)((uint32_t)hccr +
+ HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
+
+ return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
+}
+
+static const struct udevice_id mx6_usb_ids[] = {
+ { .compatible = "fsl,imx27-usb" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_mx6) = {
+ .name = "ehci_mx6",
+ .id = UCLASS_USB,
+ .of_match = mx6_usb_ids,
+ .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .bind = ehci_usb_bind,
+ .probe = ehci_usb_probe,
+ .remove = ehci_deregister,
+ .ops = &ehci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif