ehci-mx5: Clean up

[oweals/u-boot.git] / drivers / usb / host / ehci-mx5.c

diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index 58cdcbedf273c013e509faf8deae3f5d5beda175..46973b01bdaca135ff94eeedb1871d6def075525 100644 (file)
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -25,14 +25,13 @@
 #include <asm/arch/iomux.h>
 
 #include "ehci.h"
-#include "ehci-core.h"
 
 #define MX5_USBOTHER_REGS_OFFSET 0x800
 
 
-#define MXC_OTG_OFFSET         0
-#define MXC_H1_OFFSET          0x200
-#define MXC_H2_OFFSET          0x400
+#define MXC_OTG_OFFSET                 0
+#define MXC_H1_OFFSET                  0x200
+#define MXC_H2_OFFSET                  0x400
 
 #define MXC_USBCTRL_OFFSET             0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET    0x8
@@ -41,23 +40,30 @@
 #define MXC_USBH2CTRL_OFFSET           0x14
 
 /* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT  (1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT  (1 << 8) /* HOST1 power mask */
+/* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OWIE_BIT         (1 << 27)
+/* OTG power mask */
+#define MXC_OTG_UCTRL_OPM_BIT          (1 << 24)
+/* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1UIE_BIT         (1 << 12)
+/* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1WIE_BIT         (1 << 11)
+/* HOST1 power mask */
+#define MXC_H1_UCTRL_H1PM_BIT          (1 << 8)
 
 /* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT      (1 << 5) /* UH1 Disable Overcurrent Event */
+/* OTG Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT     (1 << 8)
+/* UH1 Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT              (1 << 5)
 
 /* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT  (1 << 4)
+#define MXC_H2_UCTRL_H2UIE_BIT         (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT         (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT          (1 << 4)
 
 /* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN            (1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
 
 /* USB pin configuration */
 #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
@@ -161,7 +167,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
                }
                break;
-       case 1: /* Host 1 Host ULPI */
+       case 1: /* Host 1 ULPI */
 #ifdef CONFIG_MX51
                /* The clock for the USBH1 ULPI port will come externally
                   from the PHY. */
@@ -172,9 +178,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 
                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                       v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+                       v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
                else
-                       v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+                       v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
@@ -188,9 +194,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
        case 2: /* Host 2 ULPI */
                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                       v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+                       v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
                else
-                       v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+                       v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
 
                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
                break;
@@ -206,7 +212,7 @@ void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
 void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
        __attribute((weak, alias("__board_ehci_hcd_postinit")));
 
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        struct usb_ehci *ehci;
 #ifdef CONFIG_MX53
@@ -221,7 +227,8 @@ int ehci_hcd_init(void)
 
        set_usboh3_clk();
        enable_usboh3_clk(1);
-       set_usb_phy2_clk();
+       set_usb_phy_clk();
+       enable_usb_phy1_clk(1);
        enable_usb_phy2_clk(1);
        mdelay(1);
 
@@ -230,9 +237,9 @@ int ehci_hcd_init(void)
 
        ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
                (0x200 * CONFIG_MXC_USB_PORT));
-       hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
-       hcor = (struct ehci_hcor *)((uint32_t)hccr +
-                       HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+       *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+       *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+                       HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
        setbits_le32(&ehci->usbmode, CM_HOST);
 
        __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
@@ -247,7 +254,7 @@ int ehci_hcd_init(void)
        return 0;
 }
 
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
 {
        return 0;
 }