Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[oweals/u-boot.git] / drivers / usb / host / ehci-fsl.c

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 77c41f3c3e4e0c9ffed8bac7c3520470b418d956..0ef6f238d5cc19d9eccca97c4547d00e8ebfdad1 100644 (file)
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -5,20 +5,7 @@
  *
  * Author: Tor Krill tor@excito.com
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -89,27 +76,6 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 
        if (!strcmp(phy_type, "utmi")) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
-#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
-               ccsr_usb_phy_t *usb_phy =
-                       (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
-               setbits_be32(&usb_phy->pllprg[1],
-                            CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN     |
-                            CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN     |
-                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI             |
-                            CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
-               setbits_be32(&usb_phy->port1.ctrl,
-                            CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
-               setbits_be32(&usb_phy->port1.drvvbuscfg,
-                            CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
-               setbits_be32(&usb_phy->port1.pwrfltcfg,
-                            CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
-               setbits_be32(&usb_phy->port2.ctrl,
-                            CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
-               setbits_be32(&usb_phy->port2.drvvbuscfg,
-                            CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
-               setbits_be32(&usb_phy->port2.pwrfltcfg,
-                            CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
-#endif
                setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
                setbits_be32(&ehci->control, UTMI_PHY_EN);
                udelay(1000); /* delay required for PHY Clk to appear */