+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DWC2_H__
#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET 21
#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE (1 << 22)
#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET 22
+#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH (1 << 24)
+#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH_OFFSET 24
#define DWC2_GUSBCFG_IC_USB_CAP (1 << 26)
#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET 26
#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE (1 << 27)
#define DWC2_PHY_TYPE_UTMI 1
#define DWC2_PHY_TYPE_ULPI 2
#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
+#ifndef CONFIG_DWC2_UTMI_WIDTH
#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
+#endif
#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */