Merge git://git.denx.de/u-boot-fsl-qoriq

[oweals/u-boot.git] / drivers / usb / gadget / dwc2_udc_otg.c

diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index 40a7125ca00322083dae37d6d6b120215fe64c6d..088811c191365adba3a4b9421fe84f8967ea81ba 100644 (file)
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -1,6 +1,6 @@
 /*
  * drivers/usb/gadget/dwc2_udc_otg.c
- * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
+ * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
  *
  * Copyright (C) 2008 for Samsung Electronics
  *
@@ -19,7 +19,7 @@
  */
 #undef DEBUG
 #include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <linux/list.h>
 #include <malloc.h>
 
@@ -46,7 +46,7 @@
 #define DEBUG_OUT_EP 0
 #define DEBUG_IN_EP 0
 
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
 
 #define EP0_CON                0
 #define EP_MASK                0xF
@@ -63,13 +63,11 @@ static char *state_names[] = {
        "WAIT_FOR_NULL_COMPLETE",
 };
 
-#define DRIVER_DESC "DWC2 HS USB OTG Device Driver, (c) Samsung Electronics"
 #define DRIVER_VERSION "15 March 2009"
 
 struct dwc2_udc        *the_controller;
 
 static const char driver_name[] = "dwc2-udc";
-static const char driver_desc[] = DRIVER_DESC;
 static const char ep0name[] = "ep0-control";
 
 /* Max packet size*/
@@ -190,7 +188,7 @@ static void udc_reinit(struct dwc2_udc *dev)
        dev->ep0state = WAIT_FOR_SETUP;
 
        /* basic endpoint records init */
-       for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
+       for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
                struct dwc2_ep *ep = &dev->ep[i];
 
                if (i != 0)
@@ -380,7 +378,7 @@ static void stop_activity(struct dwc2_udc *dev,
        dev->gadget.speed = USB_SPEED_UNKNOWN;
 
        /* prevent new request submissions, kill any outstanding requests  */
-       for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
+       for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
                struct dwc2_ep *ep = &dev->ep[i];
                ep->stopped = 1;
                nuke(ep, -ESHUTDOWN);
@@ -403,6 +401,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
        int i;
        unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
        uint32_t dflt_gusbcfg;
+       uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
 
        debug("Reseting OTG controller\n");
 
@@ -415,7 +414,11 @@ static void reconfig_usbd(struct dwc2_udc *dev)
                |0<<7           /* Ulpi DDR sel*/
                |0<<6           /* 0: high speed utmi+, 1: full speed serial*/
                |0<<4           /* 0: utmi+, 1:ulpi*/
+#ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
+               |0<<3           /* phy i/f  0:8bit, 1:16bit*/
+#else
                |1<<3           /* phy i/f  0:8bit, 1:16bit*/
+#endif
                |0x7<<0;        /* HS/FS Timeout**/
 
        if (dev->pdata->usb_gusbcfg)
@@ -448,7 +451,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
        writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
        writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
 
-       for (i = 1; i < S3C_MAX_ENDPOINTS; i++) {
+       for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
                writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
                writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
        }
@@ -463,29 +466,38 @@ static void reconfig_usbd(struct dwc2_udc *dev)
        /* 10. Unmask device IN EP common interrupts*/
        writel(DIEPMSK_INIT, &reg->diepmsk);
 
+       rx_fifo_sz = RX_FIFO_SIZE;
+       np_tx_fifo_sz = NPTX_FIFO_SIZE;
+       tx_fifo_sz = PTX_FIFO_SIZE;
+
+       if (dev->pdata->rx_fifo_sz)
+               rx_fifo_sz = dev->pdata->rx_fifo_sz;
+       if (dev->pdata->np_tx_fifo_sz)
+               np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
+       if (dev->pdata->tx_fifo_sz)
+               tx_fifo_sz = dev->pdata->tx_fifo_sz;
+
        /* 11. Set Rx FIFO Size (in 32-bit words) */
-       writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
+       writel(rx_fifo_sz, &reg->grxfsiz);
 
        /* 12. Set Non Periodic Tx FIFO Size */
-       writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
+       writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
               &reg->gnptxfsiz);
 
-       for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++)
-               writel((PTX_FIFO_SIZE >> 2) << 16 |
-                      ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
-                        PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
-                      &reg->dieptxf[i-1]);
+       for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
+               writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
+                       tx_fifo_sz << 16, &reg->dieptxf[i-1]);
 
        /* Flush the RX FIFO */
        writel(RX_FIFO_FLUSH, &reg->grstctl);
        while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
-               debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
+               debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
 
        /* Flush all the Tx FIFO's */
        writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
        writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
        while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
-               debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
+               debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
 
        /* 13. Clear NAK bit of EP0, EP1, EP2*/
        /* For Slave mode*/
@@ -515,7 +527,7 @@ static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed)
        }
 
        dev->ep[0].ep.maxpacket = ep0_fifo_size;
-       for (i = 1; i < S3C_MAX_ENDPOINTS; i++)
+       for (i = 1; i < DWC2_MAX_ENDPOINTS; i++)
                dev->ep[i].ep.maxpacket = ep_fifo_size;
 
        /* EP0 - Control IN (64 bytes)*/
@@ -557,8 +569,8 @@ static int dwc2_ep_enable(struct usb_ep *_ep,
        }
 
        /* hardware _could_ do smaller, but driver doesn't */
-       if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
-            && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) !=
+       if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK &&
+            le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) >
             ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
 
                debug("%s: bad %s maxpacket\n", __func__, _ep->name);
@@ -797,7 +809,7 @@ static struct dwc2_udc memory = {
  *     probe - binds to the platform device
  */
 
-int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
+int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
 {
        struct dwc2_udc *dev = &memory;
        int retval = 0;
@@ -823,7 +835,7 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
                            ROUND(sizeof(struct usb_ctrlrequest),
                                  CONFIG_SYS_CACHELINE_SIZE));
        if (!usb_ctrl) {
-               error("No memory available for UDC!\n");
+               pr_err("No memory available for UDC!\n");
                return -ENOMEM;
        }