Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).

[oweals/u-boot.git] / drivers / tsec.h

diff --git a/drivers/tsec.h b/drivers/tsec.h
index d1c70aa89f1c903a6b84344ab345b67c4b92bdd9..b55b2992b226f921a889bcf4a4c3338116668952 100644 (file)
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -18,17 +18,30 @@
 #define __TSEC_H
 
 #include <net.h>
-#include <mpc85xx.h>
+#include <config.h>
+
+#ifndef CFG_TSEC1_OFFSET
+    #define CFG_TSEC1_OFFSET   (0x24000)
+#endif
 
-#define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
 #define TSEC_SIZE      0x01000
 
+/* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
+#if defined(CONFIG_MPC85xx)
+    #define TSEC_BASE_ADDR     (CFG_IMMR + CFG_TSEC1_OFFSET)
+#elif defined(CONFIG_MPC83XX)
+    #define TSEC_BASE_ADDR     (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#endif
+
+
 #define MAC_ADDR_LEN 6
 
 /* #define TSEC_TIMEOUT        1000000 */
 #define TSEC_TIMEOUT 1000
 #define TOUT_LOOP      1000000
 
+#define PHY_AUTONEGOTIATE_TIMEOUT      5000 /* in ms */
+
 /* MAC register bits */
 #define MACCFG1_SOFT_RESET     0x80000000
 #define MACCFG1_RESET_RX_MC    0x00080000
@@ -66,6 +79,7 @@
 #define MIIM_CONTROL            0x00
 #define MIIM_CONTROL_RESET     0x00009140
 #define MIIM_CONTROL_INIT       0x00001140
+#define MIIM_CONTROL_RESTART    0x00001340
 #define MIIM_ANEN               0x00001000
 
 #define MIIM_CR                 0x00
@@ -75,6 +89,8 @@
 #define MIIM_STATUS            0x1
 #define MIIM_STATUS_AN_DONE    0x00000020
 #define MIIM_STATUS_LINK       0x0004
+#define PHY_BMSR_AUTN_ABLE     0x0008
+#define PHY_BMSR_AUTN_COMP     0x0020
 
 #define MIIM_PHYIR1            0x2
 #define MIIM_PHYIR2            0x3
@@ -108,7 +124,7 @@
 /* Cicada 8204 Extended PHY Control Register 1 */
 #define MIIM_CIS8204_EPHY_CON          0x17
 #define MIIM_CIS8204_EPHYCON_INIT      0x0006
-#define MIIM_CIS8204_EPHYCON_RGMII     0x1000
+#define MIIM_CIS8204_EPHYCON_RGMII     0x1100
 
 /* Cicada 8204 Serial LED Control Register */
 #define MIIM_CIS8204_SLED_CON          0x1b
@@ -145,12 +161,22 @@
 #define MIIM_DM9161_10BTCSR_INIT       0x7800
 
 /* LXT971 Status 2 registers */
-#define MIIM_LXT971_SR2        17  /* Status Register 2  */
-#define MIIM_LXT971_SR2_SPEED_MASK     0xf000
-#define MIIM_LXT971_SR2_10HDX  0x1000  /* 10 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_10FDX  0x2000  /* 10 Mbit full duplex selected */
-#define MIIM_LXT971_SR2_100HDX 0x4000  /* 100 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_100FDX 0x8000  /* 100 Mbit full duplex selected */
+#define MIIM_LXT971_SR2              0x11  /* Status Register 2  */
+#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
+#define MIIM_LXT971_SR2_10HDX      0x0000  /*  10 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_10FDX      0x0200  /*  10 Mbit full duplex selected */
+#define MIIM_LXT971_SR2_100HDX     0x4000  /* 100 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_100FDX     0x4200  /* 100 Mbit full duplex selected */
+
+/* DP83865 Control register values */
+#define MIIM_DP83865_CR_INIT   0x9200
+
+/* DP83865 Link and Auto-Neg Status Register */
+#define MIIM_DP83865_LANR      0x11
+#define MIIM_DP83865_SPD_MASK  0x0018
+#define MIIM_DP83865_SPD_1000  0x0010
+#define MIIM_DP83865_SPD_100   0x0008
+#define MIIM_DP83865_DPX_FULL  0x0002
 
 #define MIIM_READ_COMMAND       0x00000001