/*
- * (C) Copyright 2013 Inc.
+ * (C) Copyright 2013 Xilinx, Inc.
* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
*
* Xilinx Zynq PS SPI controller driver (master mode only)
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <config.h>
#include <common.h>
#include <dm.h>
-#include <errno.h>
#include <malloc.h>
#include <spi.h>
-#include <fdtdec.h>
#include <asm/io.h>
-#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
-#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */
-#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */
-#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */
-#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */
-#define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */
-#define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */
-#define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */
-#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */
-#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */
-#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */
-#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */
+#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
+#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
+#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
+#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
+#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
/* zynq spi priv */
struct zynq_spi_priv {
struct zynq_spi_regs *regs;
+ u8 cs;
u8 mode;
u8 fifo_depth;
u32 freq; /* required frequency */
{
struct zynq_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
u32 confr;
/* Disable SPI */
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
+ confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
+ writel(~confr, ®s->enr);
/* Disable Interrupts */
writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr);
return 0;
}
-static void spi_cs_activate(struct udevice *dev, uint cs)
+static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
struct zynq_spi_priv *priv = dev_get_priv(bus);
* xx01 - cs1
* x011 - cs2
*/
- cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
+ cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
writel(cr, ®s->cr);
}
struct udevice *bus = dev->parent;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
+ u32 confr;
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
+ confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
+ writel(~confr, ®s->enr);
return 0;
}
return -1;
}
+ priv->cs = slave_plat->cs;
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(dev, slave_plat->cs);
+ spi_cs_activate(dev);
while (rx_len > 0) {
/* Write the data into TX FIFO - tx threshold is fifo_depth */
/* Read the data from RX FIFO */
status = readl(®s->isr);
- while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
+ while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
buf = readl(®s->rxdr);
if (rx_buf)
*rx_buf++ = buf;
baud_rate_val++;
plat->speed_hz = speed / (2 << baud_rate_val);
}
- confr &= ~ZYNQ_SPI_CR_BRD_MASK;
+ confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
writel(confr, ®s->cr);
static const struct udevice_id zynq_spi_ids[] = {
{ .compatible = "xlnx,zynq-spi-r1p6" },
+ { .compatible = "cdns,spi-r1p6" },
{ }
};