rockchip: rk3288: sdram: style fixes from rk3188 sdram review

[oweals/u-boot.git] / drivers / spi / zynq_spi.c

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 04d4b71e71059b607883872593327663938e47f4..5a9b1f0f2ee4cc369c1da3b1b655ae7e5d7f540d 100644 (file)
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2013 Inc.
+ * (C) Copyright 2013 Xilinx, Inc.
  * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  *
  * Xilinx Zynq PS SPI controller driver (master mode only)
@@ -7,30 +7,26 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
-#include <config.h>
 #include <common.h>
 #include <dm.h>
-#include <errno.h>
 #include <malloc.h>
 #include <spi.h>
-#include <fdtdec.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
-#define ZYNQ_SPI_CR_MSA_MASK           (1 << 15)       /* Manual start enb */
-#define ZYNQ_SPI_CR_MCS_MASK           (1 << 14)       /* Manual chip select */
-#define ZYNQ_SPI_CR_CS_MASK            (0xF << 10)     /* Chip select */
-#define ZYNQ_SPI_CR_BAUD_MASK          (0x7 << 3)      /* Baud rate div */
-#define ZYNQ_SPI_CR_CPHA_MASK          (1 << 2)        /* Clock phase */
-#define ZYNQ_SPI_CR_CPOL_MASK          (1 << 1)        /* Clock polarity */
-#define ZYNQ_SPI_CR_MSTREN_MASK                (1 << 0)        /* Mode select */
-#define ZYNQ_SPI_IXR_RXNEMPTY_MASK     (1 << 4)        /* RX_FIFO_not_empty */
-#define ZYNQ_SPI_IXR_TXOW_MASK         (1 << 2)        /* TX_FIFO_not_full */
-#define ZYNQ_SPI_IXR_ALL_MASK          0x7F            /* All IXR bits */
-#define ZYNQ_SPI_ENR_SPI_EN_MASK       (1 << 0)        /* SPI Enable */
+#define ZYNQ_SPI_CR_MSA_MASK           BIT(15) /* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK           BIT(14) /* Manual chip select */
+#define ZYNQ_SPI_CR_CS_MASK            GENMASK(13, 10) /* Chip select */
+#define ZYNQ_SPI_CR_BAUD_MASK          GENMASK(5, 3)   /* Baud rate div */
+#define ZYNQ_SPI_CR_CPHA_MASK          BIT(2)  /* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK          BIT(1)  /* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASK                BIT(0)  /* Mode select */
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK     BIT(4)  /* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK         BIT(2)  /* TX_FIFO_not_full */
+#define ZYNQ_SPI_IXR_ALL_MASK          GENMASK(6, 0)   /* All IXR bits */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK       BIT(0)  /* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX           8       /* Baud rate divisor max val */
 #define ZYNQ_SPI_CR_BAUD_SHIFT         3       /* Baud rate divisor shift */
@@ -65,6 +61,7 @@ struct zynq_spi_platdata {
 /* zynq spi priv */
 struct zynq_spi_priv {
        struct zynq_spi_regs *regs;
+       u8 cs;
        u8 mode;
        u8 fifo_depth;
        u32 freq;               /* required frequency */
@@ -74,7 +71,7 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
 {
        struct zynq_spi_platdata *plat = bus->platdata;
        const void *blob = gd->fdt_blob;
-       int node = bus->of_offset;
+       int node = dev_of_offset(bus);
 
        plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
 
@@ -95,7 +92,8 @@ static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
        u32 confr;
 
        /* Disable SPI */
-       writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
+       confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
+       writel(~confr, &regs->enr);
 
        /* Disable Interrupts */
        writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
@@ -132,7 +130,7 @@ static int zynq_spi_probe(struct udevice *bus)
        return 0;
 }
 
-static void spi_cs_activate(struct udevice *dev, uint cs)
+static void spi_cs_activate(struct udevice *dev)
 {
        struct udevice *bus = dev->parent;
        struct zynq_spi_priv *priv = dev_get_priv(bus);
@@ -147,7 +145,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs)
         * xx01 - cs1
         * x011 - cs2
         */
-       cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
+       cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
        writel(cr, &regs->cr);
 }
 
@@ -176,8 +174,10 @@ static int zynq_spi_release_bus(struct udevice *dev)
        struct udevice *bus = dev->parent;
        struct zynq_spi_priv *priv = dev_get_priv(bus);
        struct zynq_spi_regs *regs = priv->regs;
+       u32 confr;
 
-       writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
+       confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
+       writel(~confr, &regs->enr);
 
        return 0;
 }
@@ -203,8 +203,9 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
                return -1;
        }
 
+       priv->cs = slave_plat->cs;
        if (flags & SPI_XFER_BEGIN)
-               spi_cs_activate(dev, slave_plat->cs);
+               spi_cs_activate(dev);
 
        while (rx_len > 0) {
                /* Write the data into TX FIFO - tx threshold is fifo_depth */
@@ -232,7 +233,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
                /* Read the data from RX FIFO */
                status = readl(&regs->isr);
-               while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
+               while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
                        buf = readl(&regs->rxdr);
                        if (rx_buf)
                                *rx_buf++ = buf;
@@ -315,6 +316,7 @@ static const struct dm_spi_ops zynq_spi_ops = {
 
 static const struct udevice_id zynq_spi_ids[] = {
        { .compatible = "xlnx,zynq-spi-r1p6" },
+       { .compatible = "cdns,spi-r1p6" },
        { }
 };