Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[oweals/u-boot.git] / drivers / spi / zynq_spi.c

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index ce8acb437eb0b25a01a7d28cb5f47de41dd147ba..09ae1be7e9875ed4d6acd2d7d0eae810561fefdb 100644 (file)
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
 #define ZYNQ_SPI_CR_MSA_MASK           BIT(15) /* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK           BIT(14) /* Manual chip select */
-#define ZYNQ_SPI_CR_CS_MASK            (0xF << 10)     /* Chip select */
-#define ZYNQ_SPI_CR_BAUD_MASK          (0x7 << 3)      /* Baud rate div */
+#define ZYNQ_SPI_CR_CS_MASK            GENMASK(13, 10) /* Chip select */
+#define ZYNQ_SPI_CR_BAUD_MASK          GENMASK(5, 3)   /* Baud rate div */
 #define ZYNQ_SPI_CR_CPHA_MASK          BIT(2)  /* Clock phase */
 #define ZYNQ_SPI_CR_CPOL_MASK          BIT(1)  /* Clock polarity */
 #define ZYNQ_SPI_CR_MSTREN_MASK                BIT(0)  /* Mode select */
 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK     BIT(4)  /* RX_FIFO_not_empty */
 #define ZYNQ_SPI_IXR_TXOW_MASK         BIT(2)  /* TX_FIFO_not_full */
-#define ZYNQ_SPI_IXR_ALL_MASK          0x7F            /* All IXR bits */
+#define ZYNQ_SPI_IXR_ALL_MASK          GENMASK(6, 0)   /* All IXR bits */
 #define ZYNQ_SPI_ENR_SPI_EN_MASK       BIT(0)  /* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX           8       /* Baud rate divisor max val */
@@ -313,6 +313,7 @@ static const struct dm_spi_ops zynq_spi_ops = {
 
 static const struct udevice_id zynq_spi_ids[] = {
        { .compatible = "xlnx,zynq-spi-r1p6" },
+       { .compatible = "cdns,spi-r1p6" },
        { }
 };