spi: ich: Add TPL support

[oweals/u-boot.git] / drivers / spi / zynq_qspi.c

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 5825c6d8f1f8fce6c015acfe79225c87a3054395..9ad1927a5d51f0bcdf783096fe73086c2de8e0f1 100644 (file)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2013 Xilinx, Inc.
  * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  *
  * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -30,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_IXR_TXOW_MASK                BIT(2)  /* TX_FIFO_not_full */
 #define ZYNQ_QSPI_IXR_ALL_MASK         GENMASK(6, 0)   /* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK      BIT(0)  /* SPI Enable */
+#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET     0x1C    /* Transmit 4-byte inst */
@@ -68,6 +68,9 @@ struct zynq_qspi_regs {
        u32 txd1r;      /* 0x80 */
        u32 txd2r;      /* 0x84 */
        u32 txd3r;      /* 0x88 */
+       u32 reserved1[5];
+       u32 lqspicfg;   /* 0xA0 */
+       u32 lqspists;   /* 0xA4 */
 };
 
 /* zynq qspi platform data */
@@ -97,7 +100,7 @@ static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
 {
        struct zynq_qspi_platdata *plat = bus->platdata;
        const void *blob = gd->fdt_blob;
-       int node = bus->of_offset;
+       int node = dev_of_offset(bus);
 
        plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
                                                              node, "reg");
@@ -143,6 +146,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
                ZYNQ_QSPI_CR_MSTREN_MASK;
        writel(confr, &regs->cr);
 
+       /* Disable the LQSPI feature */
+       confr = readl(&regs->lqspicfg);
+       confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
+       writel(confr, &regs->lqspicfg);
+
        /* Enable SPI */
        writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 }
@@ -478,7 +486,7 @@ static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
                break;
        }
 
-       return 0;
+       return status;
 }
 
 static int zynq_qspi_claim_bus(struct udevice *dev)