#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/omap_gpio.h>
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT 2000000
#define MM_SWITCH 0x01
#define MEM_CS 0x100
#define MEM_CS_UNSELECT 0xfffff0ff
-#define MMAP_START_ADDR 0x5c000000
+#define MMAP_START_ADDR_DRA 0x5c000000
+#define MMAP_START_ADDR_AM43x 0x30000000
#define CORE_CTRL_IO 0x4a002558
#define QSPI_CMD_READ (0x3 << 0)
struct spi_slave *slave = &qslave->slave;
u32 memval = 0;
- slave->memory_map = (void *)MMAP_START_ADDR;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+ slave->memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+ slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
+ slave->op_mode_rx = 8;
+#endif
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
+ memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_8_BITS |
+ QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS);
+#else
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
QSPI_NUM_DUMMY_BITS;
+#endif
writel(memval, &qslave->base->setup0);
}
{
struct ti_qspi_slave *qslave;
+#ifdef CONFIG_AM43XX
+ gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
+ gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
if (!qslave) {
printf("SPI_error: Fail to allocate ti_qspi_slave\n");
const uchar *txp = dout;
uchar *rxp = din;
uint status;
- int timeout, val;
+ int timeout;
+
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+ int val;
+#endif
debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
slave->bus, slave->cs, bitlen, words, flags);
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
writel(MM_SWITCH, &qslave->base->memswitch);
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
val = readl(CORE_CTRL_IO);
val |= MEM_CS;
writel(val, CORE_CTRL_IO);
+#endif
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
writel(~MM_SWITCH, &qslave->base->memswitch);
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
val = readl(CORE_CTRL_IO);
val &= MEM_CS_UNSELECT;
writel(val, CORE_CTRL_IO);
+#endif
return 0;
}
qslave->cmd |= QSPI_3_PIN;
qslave->cmd |= 0xfff;
+/* FIXME: This delay is required for successfull
+ * completion of read/write/erase. Once its root
+ * caused, it will be remove from the driver.
+ */
+#ifdef CONFIG_AM43XX
+ udelay(100);
+#endif
while (words--) {
if (txp) {
debug("tx cmd %08x dc %08x data %02x\n",
qslave->cmd |= QSPI_RD_SNGL;
debug("rx cmd %08x dc %08x\n",
qslave->cmd, qslave->dc);
+ #ifdef CONFIG_DRA7XX
+ udelay(500);
+ #endif
writel(qslave->cmd, &qslave->base->cmd);
status = readl(&qslave->base->status);
timeout = QSPI_TIMEOUT;