spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses

[oweals/u-boot.git] / drivers / spi / rk_spi.c

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index c807d78185722adeb569b4a8c0a2bd348c755ac8..95eeb8307ad245905b8c7b066cac500b49d4c62b 100644 (file)
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -2,6 +2,8 @@
 /*
  * spi driver for rockchip
  *
+ * (C) 2019 Theobroma Systems Design und Consulting GmbH
+ *
  * (C) Copyright 2015 Google, Inc
  *
  * (C) Copyright 2008-2013 Rockchip Electronics
@@ -14,16 +16,28 @@
 #include <dt-structs.h>
 #include <errno.h>
 #include <spi.h>
+#include <time.h>
 #include <linux/errno.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
 #include <dm/pinctrl.h>
 #include "rk_spi.h"
 
 /* Change to 1 to output registers at the start of each transaction */
 #define DEBUG_RK_SPI   0
 
+/*
+ * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
+ * the controller seems to hang when given 0x10000, so stick with this for now.
+ */
+#define ROCKCHIP_SPI_MAX_TRANLEN               0xffff
+
+struct rockchip_spi_params {
+       /* RXFIFO overruns and TXFIFO underruns stop the master clock */
+       bool master_manages_fifo;
+};
+
 struct rockchip_spi_platdata {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
        struct dtd_rockchip_rk3288_spi of_plat;
@@ -333,6 +347,83 @@ static int rockchip_spi_release_bus(struct udevice *dev)
        return 0;
 }
 
+static inline int rockchip_spi_16bit_reader(struct udevice *dev,
+                                           u8 **din, int *len)
+{
+       struct udevice *bus = dev->parent;
+       const struct rockchip_spi_params * const data =
+               (void *)dev_get_driver_data(bus);
+       struct rockchip_spi_priv *priv = dev_get_priv(bus);
+       struct rockchip_spi *regs = priv->regs;
+       const u32 saved_ctrlr0 = readl(&regs->ctrlr0);
+#if defined(DEBUG)
+       u32 statistics_rxlevels[33] = { };
+#endif
+       u32 frames = *len / 2;
+       u8 *in = (u8 *)(*din);
+       u32 max_chunk_size = SPI_FIFO_DEPTH;
+
+       if (!frames)
+               return 0;
+
+       /*
+        * If we know that the hardware will manage RXFIFO overruns
+        * (i.e. stop the SPI clock until there's space in the FIFO),
+        * we the allow largest possible chunk size that can be
+        * represented in CTRLR1.
+        */
+       if (data && data->master_manages_fifo)
+               max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
+
+       // rockchip_spi_configure(dev, mode, size)
+       rkspi_enable_chip(regs, false);
+       clrsetbits_le32(&regs->ctrlr0,
+                       TMOD_MASK << TMOD_SHIFT,
+                       TMOD_RO << TMOD_SHIFT);
+       /* 16bit data frame size */
+       clrsetbits_le32(&regs->ctrlr0, DFS_MASK, DFS_16BIT);
+
+       /* Update caller's context */
+       const u32 bytes_to_process = 2 * frames;
+       *din += bytes_to_process;
+       *len -= bytes_to_process;
+
+       /* Process our frames */
+       while (frames) {
+               u32 chunk_size = min(frames, max_chunk_size);
+
+               frames -= chunk_size;
+
+               writew(chunk_size - 1, &regs->ctrlr1);
+               rkspi_enable_chip(regs, true);
+
+               do {
+                       u32 rx_level = readw(&regs->rxflr);
+#if defined(DEBUG)
+                       statistics_rxlevels[rx_level]++;
+#endif
+                       chunk_size -= rx_level;
+                       while (rx_level--) {
+                               u16 val = readw(regs->rxdr);
+                               *in++ = val & 0xff;
+                               *in++ = val >> 8;
+                       }
+               } while (chunk_size);
+
+               rkspi_enable_chip(regs, false);
+       }
+
+#if defined(DEBUG)
+       debug("%s: observed rx_level during processing:\n", __func__);
+       for (int i = 0; i <= 32; ++i)
+               if (statistics_rxlevels[i])
+                       debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
+#endif
+       /* Restore the original transfer setup and return error-free. */
+       writel(saved_ctrlr0, &regs->ctrlr0);
+       return 0;
+}
+
 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
                           const void *dout, void *din, unsigned long flags)
 {
@@ -344,7 +435,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
        const u8 *out = dout;
        u8 *in = din;
        int toread, towrite;
-       int ret;
+       int ret = 0;
 
        debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
              len, flags);
@@ -355,8 +446,18 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
        if (flags & SPI_XFER_BEGIN)
                spi_cs_activate(dev, slave_plat->cs);
 
+       /*
+        * To ensure fast loading of firmware images (e.g. full U-Boot
+        * stage, ATF, Linux kernel) from SPI flash, we optimise the
+        * case of read-only transfers by using the full 16bits of each
+        * FIFO element.
+        */
+       if (!out)
+               ret = rockchip_spi_16bit_reader(dev, &in, &len);
+
+       /* This is the original 8bit reader/writer code */
        while (len > 0) {
-               int todo = min(len, 0x10000);
+               int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
 
                rkspi_enable_chip(regs, false);
                writel(todo - 1, &regs->ctrlr1);
@@ -437,10 +538,16 @@ static const struct dm_spi_ops rockchip_spi_ops = {
         */
 };
 
+const  struct rockchip_spi_params rk3399_spi_params = {
+       .master_manages_fifo = true,
+};
+
 static const struct udevice_id rockchip_spi_ids[] = {
        { .compatible = "rockchip,rk3288-spi" },
-       { .compatible = "rockchip,rk3368-spi" },
-       { .compatible = "rockchip,rk3399-spi" },
+       { .compatible = "rockchip,rk3368-spi",
+         .data = (ulong)&rk3399_spi_params },
+       { .compatible = "rockchip,rk3399-spi",
+         .data = (ulong)&rk3399_spi_params },
        { }
 };