#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/imx-common/spi.h>
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
MXC_SPI_BASE_ADDRESSES
};
+__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return -1;
+}
+
#define OUT MXC_GPIO_DIRECTION_OUT
#define reg_read readl
#define reg_write(a, v) writel(v, a)
+#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
+#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
+#endif
+
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
#endif
int gpio;
int ss_pol;
+ unsigned int max_hz;
+ unsigned int mode;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
}
#ifdef MXC_CSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
unsigned int ctrl_reg;
u32 clk_src;
u32 div;
+ unsigned int max_hz = mxcs->max_hz;
+ unsigned int mode = mxcs->mode;
clk_src = mxc_get_clock(MXC_CSPI_CLK);
#endif
#ifdef MXC_ECSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
s32 reg_ctrl, reg_config;
u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
u32 pre_div = 0, post_div = 0;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
-
- if (max_hz == 0) {
- printf("Error: desired clock is 0\n");
- return -1;
- }
+ unsigned int max_hz = mxcs->max_hz;
+ unsigned int mode = mxcs->mode;
/*
* Reset SPI and set all CSs to master mode, if toggling
reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
- /* We need to disable SPI before changing registers */
- reg_ctrl &= ~MXC_CSPICTRL_EN;
-
if (mode & SPI_CS_HIGH)
ss_pol = 1;
int nbytes = DIV_ROUND_UP(bitlen, 8);
u32 data, cnt, i;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
+ u32 ts;
+ int status;
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
__func__, bitlen, (u32)dout, (u32)din);
reg_write(®s->ctrl, mxcs->ctrl_reg |
MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
+ ts = get_timer(0);
+ status = reg_read(®s->stat);
/* Wait until the TC (Transfer completed) bit is set */
- while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0)
- ;
+ while ((status & MXC_CSPICTRL_TC) == 0) {
+ if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
+ printf("spi_xchg_single: Timeout!\n");
+ return -1;
+ }
+ status = reg_read(®s->stat);
+ }
/* Transfer completed, clear any pending request */
reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
tmp = reg_read(®s->rxdata);
data = cpu_to_be32(tmp);
debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
- cnt = min(nbytes, sizeof(data));
+ cnt = min_t(u32, nbytes, sizeof(data));
if (din) {
memcpy(din, &data, cnt);
din += cnt;
{
}
-static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
+/*
+ * Some SPI devices require active chip-select over multiple
+ * transactions, we achieve this using a GPIO. Still, the SPI
+ * controller has to be configured to use one of its own chipselects.
+ * To use this feature you have to implement board_spi_cs_gpio() to assign
+ * a gpio value for each cs (-1 if cs doesn't need to use gpio).
+ * You must use some unused on this SPI controller cs between 0 and 3.
+ */
+static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
+ unsigned int bus, unsigned int cs)
{
int ret;
- /*
- * Some SPI devices require active chip-select over multiple
- * transactions, we achieve this using a GPIO. Still, the SPI
- * controller has to be configured to use one of its own chipselects.
- * To use this feature you have to call spi_setup_slave() with
- * cs = internal_cs | (gpio << 8), and you have to use some unused
- * on this SPI controller cs between 0 and 3.
- */
- if (cs > 3) {
- mxcs->gpio = cs >> 8;
- cs &= 3;
- ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
- if (ret) {
- printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
- return -EINVAL;
- }
- } else {
- mxcs->gpio = -1;
+ mxcs->gpio = board_spi_cs_gpio(bus, cs);
+ if (mxcs->gpio == -1)
+ return 0;
+
+ ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
+ if (ret) {
+ printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
+ return -EINVAL;
}
- return cs;
+ return 0;
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (bus >= ARRAY_SIZE(spi_bases))
return NULL;
+ if (max_hz == 0) {
+ printf("Error: desired clock is 0\n");
+ return NULL;
+ }
+
mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
if (!mxcs) {
puts("mxc_spi: SPI Slave not allocated !\n");
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
- ret = decode_cs(mxcs, cs);
+ ret = setup_cs_gpio(mxcs, bus, cs);
if (ret < 0) {
free(mxcs);
return NULL;
}
- cs = ret;
-
mxcs->base = spi_bases[bus];
+ mxcs->max_hz = max_hz;
+ mxcs->mode = mode;
- ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
- if (ret) {
- printf("mxc_spi: cannot setup SPI controller\n");
- free(mxcs);
- return NULL;
- }
return &mxcs->slave;
}
int spi_claim_bus(struct spi_slave *slave)
{
+ int ret;
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
reg_write(®s->rxdata, 1);
udelay(1);
- reg_write(®s->ctrl, mxcs->ctrl_reg);
+ ret = spi_cfg_mxc(mxcs, slave->cs);
+ if (ret) {
+ printf("mxc_spi: cannot setup SPI controller\n");
+ return ret;
+ }
reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
reg_write(®s->intr, 0);