return 0;
}
+static int ich_spi_remove(struct udevice *bus)
+{
+ struct ich_spi_priv *ctlr = dev_get_priv(bus);
+
+ /*
+ * Configure SPI controller so that the Linux MTD driver can fully
+ * access the SPI NOR chip
+ */
+ ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
+ ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
+ ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
+ ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
+
+ return 0;
+}
+
static int ich_spi_set_speed(struct udevice *bus, uint speed)
{
struct ich_spi_priv *priv = dev_get_priv(bus);
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
*/
- if (plat->ich_version == ICHV_7) {
- slave->mode_rx = SPI_RX_SLOW;
- slave->mode = SPI_TX_BYTE;
- }
+ if (plat->ich_version == ICHV_7)
+ slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
return 0;
}
static int ich_spi_ofdata_to_platdata(struct udevice *dev)
{
struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ int node = dev_of_offset(dev);
int ret;
- ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
- "intel,ich7-spi");
+ ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi");
if (ret == 0) {
plat->ich_version = ICHV_7;
} else {
- ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
+ ret = fdt_node_check_compatible(gd->fdt_blob, node,
"intel,ich9-spi");
if (ret == 0)
plat->ich_version = ICHV_9;
.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
.child_pre_probe = ich_spi_child_pre_probe,
.probe = ich_spi_probe,
+ .remove = ich_spi_remove,
+ .flags = DM_FLAG_OS_PREPARE,
};