/*
* Copyright (c) 2011-12 The Chromium OS Authors.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*
* This file is derived from the flashrom project.
*/
return NULL;
}
+ /*
+ * Yes this controller can only write a small number of bytes at
+ * once! The limit is typically 64 bytes.
+ */
+ ich->slave.max_write_size = ctlr.databytes;
ich->speed = max_hz;
+ /*
+ * ICH 7 SPI controller only supports array read command
+ * and byte program command for SST flash
+ */
+ if (ctlr.ich_version == 7) {
+ ich->slave.op_mode_rx = SPI_OPM_RX_AS;
+ ich->slave.op_mode_tx = SPI_OPM_TX_BP;
+ }
+
return &ich->slave;
}
*/
static int get_ich_version(uint16_t device_id)
{
- if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
+ if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
+ device_id == PCI_DEVICE_ID_INTEL_ITC_LPC)
return 7;
if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
/*
* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
- * below is True) or 0. In case the wait was for the bit(s) to set - write
+ * below is true) or 0. In case the wait was for the bit(s) to set - write
* those bits back, which would cause resetting them.
*
* Return the last read status value on success or -1 on failure.
struct spi_trans *trans = &ich->trans;
unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
int using_cmd = 0;
- /* Align read transactions to 64-byte boundaries */
- char buff[ctlr.databytes];
/* Ee don't support writing partial bytes. */
if (bitlen % 8) {
*/
while (trans->bytesout || trans->bytesin) {
uint32_t data_length;
- uint32_t aligned_offset;
- uint32_t diff;
-
- aligned_offset = trans->offset & ~(ctlr.databytes - 1);
- diff = trans->offset - aligned_offset;
/* SPI addresses are 24 bit only */
- ich_writel(aligned_offset & 0x00FFFFFF, ctlr.addr);
+ ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr);
if (trans->bytesout)
data_length = min(trans->bytesout, ctlr.databytes);
}
if (trans->bytesin) {
- if (diff) {
- data_length -= diff;
- read_reg(ctlr.data, buff, ctlr.databytes);
- memcpy(trans->in, buff + diff, data_length);
- } else {
- read_reg(ctlr.data, trans->in, data_length);
- }
+ read_reg(ctlr.data, trans->in, data_length);
spi_use_in(trans, data_length);
if (with_address)
trans->offset += data_length;