#include <spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
+#include <linux/iopoll.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
-#define RX_BUFFER_SIZE 0x80
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
-#define TX_BUFFER_SIZE 0x200
-#else
-#define TX_BUFFER_SIZE 0x40
-#endif
-
#define OFFSET_BITS_MASK GENMASK(23, 0)
#define FLASH_STATUS_WEL 0x02
/* QSPI max chipselect signals number */
#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
-#ifdef CONFIG_DM_SPI
+/* Controller needs driver to swap endian */
+#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
+
+enum fsl_qspi_devtype {
+ FSL_QUADSPI_VYBRID,
+ FSL_QUADSPI_IMX6SX,
+ FSL_QUADSPI_IMX6UL_7D,
+ FSL_QUADSPI_IMX7ULP,
+};
+
+struct fsl_qspi_devtype_data {
+ enum fsl_qspi_devtype devtype;
+ u32 rxfifo;
+ u32 txfifo;
+ u32 ahb_buf_size;
+ u32 driver_data;
+};
+
/**
* struct fsl_qspi_platdata - platform data for Freescale QSPI
*
u32 flash_num;
u32 num_chipselect;
};
-#endif
/**
* struct fsl_qspi_priv - private data for Freescale QSPI
u32 flash_num;
u32 num_chipselect;
struct fsl_qspi_regs *regs;
+ struct fsl_qspi_devtype_data *devtype_data;
};
-#ifndef CONFIG_DM_SPI
-struct fsl_qspi {
- struct spi_slave slave;
- struct fsl_qspi_priv priv;
+static const struct fsl_qspi_devtype_data vybrid_data = {
+ .devtype = FSL_QUADSPI_VYBRID,
+ .rxfifo = 128,
+ .txfifo = 64,
+ .ahb_buf_size = 1024,
+ .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
+};
+
+static const struct fsl_qspi_devtype_data imx6sx_data = {
+ .devtype = FSL_QUADSPI_IMX6SX,
+ .rxfifo = 128,
+ .txfifo = 512,
+ .ahb_buf_size = 1024,
+ .driver_data = 0,
+};
+
+static const struct fsl_qspi_devtype_data imx6ul_7d_data = {
+ .devtype = FSL_QUADSPI_IMX6UL_7D,
+ .rxfifo = 128,
+ .txfifo = 512,
+ .ahb_buf_size = 1024,
+ .driver_data = 0,
+};
+
+static const struct fsl_qspi_devtype_data imx7ulp_data = {
+ .devtype = FSL_QUADSPI_IMX7ULP,
+ .rxfifo = 64,
+ .txfifo = 64,
+ .ahb_buf_size = 128,
+ .driver_data = 0,
};
-#endif
static u32 qspi_read32(u32 flags, u32 *addr)
{
static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
{
u32 val;
- const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
- QSPI_SR_IP_ACC_MASK;
- unsigned int retry = 5;
+ u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
+ QSPI_SR_IP_ACC_MASK;
- do {
- val = qspi_read32(priv->flags, &priv->regs->sr);
-
- if ((~val & mask) == mask)
- return 0;
+ if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
+ mask = (u32)cpu_to_be32(mask);
- udelay(1);
- } while (--retry);
-
- return -ETIMEDOUT;
+ return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
}
/* QSPI support swapping the flash read/write data
* in hardware for LS102xA, but not for VF610 */
-static inline u32 qspi_endian_xchg(u32 data)
+static inline u32 qspi_endian_xchg(struct fsl_qspi_priv *priv, u32 data)
{
-#ifdef CONFIG_VF610
- return swab32(data);
-#else
- return data;
-#endif
+ if (priv->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN)
+ return swab32(data);
+ else
+ return data;
}
static void qspi_set_lut(struct fsl_qspi_priv *priv)
#endif
qspi_write32(priv->flags, ®s->lut[lut_base + 1],
OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
- OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
+ OPRND1(priv->devtype_data->rxfifo) | PAD1(LUT_PAD1) |
INSTR1(LUT_READ));
qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#endif
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
- /*
- * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
- * So, Use IDATSZ in IPCR to determine the size and here set 0.
- */
+ /* Use IDATSZ in IPCR to determine the size and here set 0. */
qspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(0) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
-#else
- qspi_write32(priv->flags, ®s->lut[lut_base + 1],
- OPRND0(TX_BUFFER_SIZE) |
- PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
-#endif
qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
{
struct fsl_qspi_regs *regs = priv->regs;
u32 mcr_reg;
- void *rx_addr = NULL;
+ void *rx_addr;
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ mcr_reg);
rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
/* Read out the data directly from the AHB buffer. */
reg |= QSPI_MCR_DDR_EN_MASK;
/* Enable bit 29 for imx6sx */
reg |= BIT(29);
-
qspi_write32(priv->flags, ®s->mcr, reg);
+
+ /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc
+ * These two bits are reserved on other platforms
+ */
+ reg = qspi_read32(priv->flags, ®s->flshcr);
+ reg &= ~(BIT(17));
+ reg |= BIT(16);
+ qspi_write32(priv->flags, ®s->flshcr, reg);
}
/*
qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
- (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
+ ((priv->devtype_data->ahb_buf_size >> 3) << QSPI_BUF3CR_ADATSZ_SHIFT));
/* We only use the buffer3 */
qspi_write32(priv->flags, ®s->buf0ind, 0);
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ mcr_reg);
qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base);
reg = qspi_read32(priv->flags, ®s->rbsr);
if (reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[0]);
- data = qspi_endian_xchg(data);
+ data = qspi_endian_xchg(priv, data);
memcpy(rxbuf, &data, len);
qspi_write32(priv->flags, ®s->mcr,
qspi_read32(priv->flags, ®s->mcr) |
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ mcr_reg);
qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base);
;
i = 0;
- while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
+ while ((priv->devtype_data->rxfifo >= len) && (len > 0)) {
WATCHDOG_RESET();
rbsr_reg = qspi_read32(priv->flags, ®s->rbsr);
if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[i]);
- data = qspi_endian_xchg(data);
+ data = qspi_endian_xchg(priv, data);
size = (len < 4) ? len : 4;
memcpy(rxbuf, &data, size);
len -= size;
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ mcr_reg);
qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
to_or_from = priv->sf_addr + priv->cur_amba_base;
qspi_write32(priv->flags, ®s->sfar, to_or_from);
- size = (len > RX_BUFFER_SIZE) ?
- RX_BUFFER_SIZE : len;
+ size = (len > priv->devtype_data->rxfifo) ?
+ priv->devtype_data->rxfifo : len;
qspi_write32(priv->flags, ®s->ipcr,
(seqid << QSPI_IPCR_SEQID_SHIFT) |
len -= size;
i = 0;
- while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
+ while ((priv->devtype_data->rxfifo >= size) && (size > 0)) {
data = qspi_read32(priv->flags, ®s->rbdr[i]);
- data = qspi_endian_xchg(data);
+ data = qspi_endian_xchg(priv, data);
if (size < 4)
memcpy(rxbuf, &data, size);
else
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ mcr_reg);
qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
status_reg = 0;
reg = qspi_read32(priv->flags, ®s->rbsr);
if (reg & QSPI_RBSR_RDBFL_MASK) {
status_reg = qspi_read32(priv->flags, ®s->rbdr[0]);
- status_reg = qspi_endian_xchg(status_reg);
+ status_reg = qspi_endian_xchg(priv, status_reg);
}
qspi_write32(priv->flags, ®s->mcr,
qspi_read32(priv->flags, ®s->mcr) |
qspi_write32(priv->flags, ®s->sfar, to_or_from);
- tx_size = (len > TX_BUFFER_SIZE) ?
- TX_BUFFER_SIZE : len;
+ tx_size = (len > priv->devtype_data->txfifo) ?
+ priv->devtype_data->txfifo : len;
size = tx_size / 16;
/*
size++;
for (i = 0; i < size * 4; i++) {
memcpy(&data, txbuf, 4);
- data = qspi_endian_xchg(data);
+ data = qspi_endian_xchg(priv, data);
qspi_write32(priv->flags, ®s->tbdr, data);
txbuf += 4;
}
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ mcr_reg);
qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base);
reg = qspi_read32(priv->flags, ®s->rbsr);
if (reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[0]);
- data = qspi_endian_xchg(data);
+ data = qspi_endian_xchg(priv, data);
memcpy(rxbuf, &data, len);
qspi_write32(priv->flags, ®s->mcr,
qspi_read32(priv->flags, ®s->mcr) |
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ mcr_reg);
qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
to_or_from = priv->sf_addr + priv->cur_amba_base;
smpr_val |= set_bits;
qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
}
-#ifndef CONFIG_DM_SPI
-static unsigned long spi_bases[] = {
- QSPI0_BASE_ADDR,
-#ifdef CONFIG_MX6SX
- QSPI1_BASE_ADDR,
-#endif
-};
-
-static unsigned long amba_bases[] = {
- QSPI0_AMBA_BASE,
-#ifdef CONFIG_MX6SX
- QSPI1_AMBA_BASE,
-#endif
-};
-
-static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct fsl_qspi, slave);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- u32 mcr_val;
- struct fsl_qspi *qspi;
- struct fsl_qspi_regs *regs;
- u32 total_size;
-
- if (bus >= ARRAY_SIZE(spi_bases))
- return NULL;
-
- if (cs >= FSL_QSPI_FLASH_NUM)
- return NULL;
-
- qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
- if (!qspi)
- return NULL;
-
-#ifdef CONFIG_SYS_FSL_QSPI_BE
- qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
-#endif
-
- regs = (struct fsl_qspi_regs *)spi_bases[bus];
- qspi->priv.regs = regs;
- /*
- * According cs, use different amba_base to choose the
- * corresponding flash devices.
- *
- * If not, only one flash device is used even if passing
- * different cs using `sf probe`
- */
- qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
-
- qspi->slave.max_write_size = TX_BUFFER_SIZE;
-
- mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr);
-
- /* Set endianness to LE for i.mx */
- if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
- mcr_val = QSPI_MCR_END_CFD_LE;
-
- qspi_write32(qspi->priv.flags, ®s->mcr,
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
- (mcr_val & QSPI_MCR_END_CFD_MASK));
-
- qspi_cfg_smpr(&qspi->priv,
- ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
- QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
-
- total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
- /*
- * Any read access to non-implemented addresses will provide
- * undefined results.
- *
- * In case single die flash devices, TOP_ADDR_MEMA2 and
- * TOP_ADDR_MEMB2 should be initialized/programmed to
- * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
- * setting the size of these devices to 0. This would ensure
- * that the complete memory map is assigned to only one flash device.
- */
- qspi_write32(qspi->priv.flags, ®s->sfa1ad,
- FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
- qspi_write32(qspi->priv.flags, ®s->sfa2ad,
- FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
- qspi_write32(qspi->priv.flags, ®s->sfb1ad,
- total_size | amba_bases[bus]);
- qspi_write32(qspi->priv.flags, ®s->sfb2ad,
- total_size | amba_bases[bus]);
-
- qspi_set_lut(&qspi->priv);
-
-#ifdef CONFIG_SYS_FSL_QSPI_AHB
- qspi_init_ahb_read(&qspi->priv);
-#endif
-
- qspi_module_disable(&qspi->priv, 0);
-
- return &qspi->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct fsl_qspi *qspi = to_qspi_spi(slave);
-
- free(qspi);
-}
-int spi_claim_bus(struct spi_slave *slave)
-{
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- /* Nothing to do */
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- struct fsl_qspi *qspi = to_qspi_spi(slave);
-
- return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
-}
-
-void spi_init(void)
-{
- /* Nothing to do */
-}
-#else
static int fsl_qspi_child_pre_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct fsl_qspi_priv *priv = dev_get_priv(dev_get_parent(dev));
- slave->max_write_size = TX_BUFFER_SIZE;
+ slave->max_write_size = priv->devtype_data->txfifo;
return 0;
}
static int fsl_qspi_probe(struct udevice *bus)
{
- u32 mcr_val;
u32 amba_size_per_chip;
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
+ priv->devtype_data = (struct fsl_qspi_devtype_data *)dev_get_driver_data(bus);
+ if (!priv->devtype_data) {
+ printf("ERROR : No devtype_data found\n");
+ return -ENODEV;
+ }
+
+ debug("devtype=%d, txfifo=%d, rxfifo=%d, ahb=%d, data=0x%x\n",
+ priv->devtype_data->devtype,
+ priv->devtype_data->txfifo,
+ priv->devtype_data->rxfifo,
+ priv->devtype_data->ahb_buf_size,
+ priv->devtype_data->driver_data);
+
/* make sure controller is not busy anywhere */
ret = is_controller_busy(priv);
return ret;
}
- mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
-
- /* Set endianness to LE for i.mx */
- if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
- mcr_val = QSPI_MCR_END_CFD_LE;
-
qspi_write32(priv->flags, &priv->regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
- (mcr_val & QSPI_MCR_END_CFD_MASK));
+ QSPI_MCR_END_CFD_LE);
qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
};
static const struct udevice_id fsl_qspi_ids[] = {
- { .compatible = "fsl,vf610-qspi" },
- { .compatible = "fsl,imx6sx-qspi" },
- { .compatible = "fsl,imx6ul-qspi" },
- { .compatible = "fsl,imx7d-qspi" },
+ { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data },
+ { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data },
+ { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data },
+ { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data },
+ { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data },
{ }
};
.probe = fsl_qspi_probe,
.child_pre_probe = fsl_qspi_child_pre_probe,
};
-#endif
projects / oweals / u-boot.git / blobdiff