spi: xilinx_spi: Fix to configure CPOL, CPHA mask

[oweals/u-boot.git] / drivers / spi / fsl_dspi.c

diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 792853192ed78fc661b467d2f5c21405f97bdd47..887edd801a42d1a87662ca7e3f0f036f19e50cc2 100644 (file)
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -654,7 +654,7 @@ static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
        plat->num_chipselect =
                fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
 
-       addr = fdtdec_get_addr(blob, node, "reg");
+       addr = dev_get_addr(bus);
        if (addr == FDT_ADDR_T_NONE) {
                debug("DSPI: Can't get base address or size\n");
                return -ENOMEM;
@@ -664,8 +664,8 @@ static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
        plat->speed_hz = fdtdec_get_int(blob,
                        node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
 
-       debug("DSPI: regs=0x%llx, max-frequency=%d, endianess=%s, num-cs=%d\n",
-             (u64)plat->regs_addr, plat->speed_hz,
+       debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
+             &plat->regs_addr, plat->speed_hz,
              plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
              plat->num_chipselect);