net: sun8i_emac: Use consistent clock bitfield definitions

[oweals/u-boot.git] / drivers / spi / designware_spi.c

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 5cca41448674aa497bd65228f2e82d25ad1122aa..c9b14f90292ec2898dce6471385d6ac390b7138a 100644 (file)
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -9,8 +9,9 @@
  * Copyright (c) 2009, Intel Corporation.
  */
 
-#include <asm-generic/gpio.h>
 #include <common.h>
+#include <log.h>
+#include <asm-generic/gpio.h>
 #include <clk.h>
 #include <dm.h>
 #include <errno.h>
@@ -18,12 +19,12 @@
 #include <spi.h>
 #include <fdtdec.h>
 #include <reset.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
 #include <linux/compat.h>
 #include <linux/iopoll.h>
 #include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /* Register offsets */
 #define DW_SPI_CTRL0                   0x00
 #define DW_SPI_CTRL1                   0x04
@@ -128,7 +129,7 @@ static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
 
 static int request_gpio_cs(struct udevice *bus)
 {
-#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
        struct dw_spi_priv *priv = dev_get_priv(bus);
        int ret;
 
@@ -155,14 +156,12 @@ static int request_gpio_cs(struct udevice *bus)
 static int dw_spi_ofdata_to_platdata(struct udevice *bus)
 {
        struct dw_spi_platdata *plat = bus->platdata;
-       const void *blob = gd->fdt_blob;
-       int node = dev_of_offset(bus);
 
        plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
 
        /* Use 500KHz as a suitable default */
-       plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
-                                       500000);
+       plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+                                              500000);
        debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
              plat->frequency);
 
@@ -369,9 +368,15 @@ static int poll_transfer(struct dw_spi_priv *priv)
        return 0;
 }
 
-static void external_cs_manage(struct udevice *dev, bool on)
+/*
+ * We define external_cs_manage function as 'weak' as some targets
+ * (like MSCC Ocelot) don't control the external CS pin using a GPIO
+ * controller. These SoCs use specific registers to control by
+ * software the SPI pins (and especially the CS).
+ */
+__weak void external_cs_manage(struct udevice *dev, bool on)
 {
-#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
        struct dw_spi_priv *priv = dev_get_priv(dev->parent);
 
        if (!dm_gpio_is_valid(&priv->cs_gpio))
@@ -516,8 +521,22 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode)
 static int dw_spi_remove(struct udevice *bus)
 {
        struct dw_spi_priv *priv = dev_get_priv(bus);
+       int ret;
+
+       ret = reset_release_bulk(&priv->resets);
+       if (ret)
+               return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+       ret = clk_disable(&priv->clk);
+       if (ret)
+               return ret;
 
-       return reset_release_bulk(&priv->resets);
+       ret = clk_free(&priv->clk);
+       if (ret)
+               return ret;
+#endif
+       return 0;
 }
 
 static const struct dm_spi_ops dw_spi_ops = {