Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[oweals/u-boot.git] / drivers / spi / cadence_qspi_apb.c

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 39e31f618cf3ad7fce2070c1a243dc066ef42dde..e02f2217f45f55c3c67da247d5b0a1332d026ff9 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -30,6 +30,7 @@
 #include <linux/errno.h>
 #include <wait_bit.h>
 #include <spi.h>
+#include <bouncebuf.h>
 #include "cadence_qspi.h"
 
 #define CQSPI_REG_POLL_US                      1 /* 1us */
@@ -169,9 +170,6 @@
        ((readl(base + CQSPI_REG_CONFIG) >>             \
                CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 
-#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)          \
-       ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
-
 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                      \
        (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
        CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
@@ -355,16 +353,20 @@ void cadence_qspi_apb_delay(void *reg_base,
        cadence_qspi_apb_controller_disable(reg_base);
 
        /* Convert to ns. */
-       ref_clk_ns = (1000000000) / ref_clk;
+       ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
 
        /* Convert to ns. */
-       sclk_ns = (1000000000) / sclk_hz;
-
-       /* Plus 1 to round up 1 clock cycle. */
-       tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
-       tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
-       tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
-       tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
+       sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
+
+       /* The controller adds additional delay to that programmed in the reg */
+       if (tshsl_ns >= sclk_ns + ref_clk_ns)
+               tshsl_ns -= sclk_ns + ref_clk_ns;
+       if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
+               tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
+       tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
+       tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
+       tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
+       tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
 
        reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
                        << CQSPI_REG_DELAY_TSHSL_LSB);
@@ -632,6 +634,8 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 {
        unsigned int remaining = n_rx;
        unsigned int bytes_to_read = 0;
+       struct bounce_buffer bb;
+       u8 *bb_rxbuf;
        int ret;
 
        writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
@@ -640,6 +644,11 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
        writel(CQSPI_REG_INDIRECTRD_START,
               plat->regbase + CQSPI_REG_INDIRECTRD);
 
+       ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
+       if (ret)
+               return ret;
+       bb_rxbuf = bb.bounce_buffer;
+
        while (remaining > 0) {
                ret = cadence_qspi_wait_for_data(plat);
                if (ret < 0) {
@@ -653,12 +662,13 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
                        bytes_to_read *= CQSPI_FIFO_WIDTH;
                        bytes_to_read = bytes_to_read > remaining ?
                                        remaining : bytes_to_read;
-                       /* Handle non-4-byte aligned access to avoid data abort. */
-                       if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
-                               readsb(plat->ahbbase, rxbuf, bytes_to_read);
-                       else
-                               readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
-                       rxbuf += bytes_to_read;
+                       readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
+                       if (bytes_to_read % 4)
+                               readsb(plat->ahbbase,
+                                      bb_rxbuf + rounddown(bytes_to_read, 4),
+                                      bytes_to_read % 4);
+
+                       bb_rxbuf += bytes_to_read;
                        remaining -= bytes_to_read;
                        bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
                }
@@ -675,6 +685,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
        /* Clear indirect completion status */
        writel(CQSPI_REG_INDIRECTRD_DONE,
               plat->regbase + CQSPI_REG_INDIRECTRD);
+       bounce_buffer_stop(&bb);
 
        return 0;
 
@@ -682,6 +693,7 @@ failrd:
        /* Cancel the indirect read */
        writel(CQSPI_REG_INDIRECTRD_CANCEL,
               plat->regbase + CQSPI_REG_INDIRECTRD);
+       bounce_buffer_stop(&bb);
        return ret;
 }
 
@@ -723,6 +735,17 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
        unsigned int remaining = n_tx;
        unsigned int write_bytes;
        int ret;
+       struct bounce_buffer bb;
+       u8 *bb_txbuf;
+
+       /*
+        * Handle non-4-byte aligned accesses via bounce buffer to
+        * avoid data abort.
+        */
+       ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
+       if (ret)
+               return ret;
+       bb_txbuf = bb.bounce_buffer;
 
        /* Configure the indirect read transfer bytes */
        writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
@@ -733,11 +756,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 
        while (remaining > 0) {
                write_bytes = remaining > page_size ? page_size : remaining;
-               /* Handle non-4-byte aligned access to avoid data abort. */
-               if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
-                       writesb(plat->ahbbase, txbuf, write_bytes);
-               else
-                       writesl(plat->ahbbase, txbuf, write_bytes >> 2);
+               writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
+               if (write_bytes % 4)
+                       writesb(plat->ahbbase,
+                               bb_txbuf + rounddown(write_bytes, 4),
+                               write_bytes % 4);
 
                ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
                                   CQSPI_REG_SDRAMLEVEL_WR_MASK <<
@@ -747,7 +770,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
                        goto failwr;
                }
 
-               txbuf += write_bytes;
+               bb_txbuf += write_bytes;
                remaining -= write_bytes;
        }
 
@@ -758,6 +781,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
                printf("Indirect write completion error (%i)\n", ret);
                goto failwr;
        }
+       bounce_buffer_stop(&bb);
 
        /* Clear indirect completion status */
        writel(CQSPI_REG_INDIRECTWR_DONE,
@@ -768,6 +792,7 @@ failwr:
        /* Cancel the indirect write */
        writel(CQSPI_REG_INDIRECTWR_CANCEL,
               plat->regbase + CQSPI_REG_INDIRECTWR);
+       bounce_buffer_stop(&bb);
        return ret;
 }