spi: cadence_qspi: Add quad write support

[oweals/u-boot.git] / drivers / spi / cadence_qspi_apb.c

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index a8af3520303537e734405f23f633019e70a7fc0e..55a7501913a8e4e22bc98001051477f611d161a6 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -77,6 +77,7 @@
 
 #define        CQSPI_REG_WR_INSTR                      0x08
 #define        CQSPI_REG_WR_INSTR_OPCODE_LSB           0
+#define        CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 
 #define        CQSPI_REG_DELAY                         0x0C
 #define        CQSPI_REG_DELAY_TSLCH_LSB               0
@@ -686,7 +687,7 @@ failrd:
 
 /* Opcode + Address (3/4 bytes) */
 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
-       unsigned int cmdlen, const u8 *cmdbuf)
+       unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf)
 {
        unsigned int reg;
        unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
@@ -702,6 +703,10 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 
        /* Configure the opcode */
        reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
+
+       if (tx_width & SPI_TX_QUAD)
+               reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
+
        writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 
        /* Setup write address. */