Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

[oweals/u-boot.git] / drivers / spi / cadence_qspi.h

diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 9106b09d2976b8d9fa6c76331052701fd45a6ec9..ae459c74a19279c9201a310f35781478cb865c26 100644 (file)
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -1,13 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012
  * Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CADENCE_QSPI_H__
 #define __CADENCE_QSPI_H__
 
+#include <reset.h>
+
 #define CQSPI_IS_ADDR(cmd_len)         (cmd_len > 1 ? 1 : 0)
 
 #define CQSPI_NO_DECODER_MAX_CS                4
@@ -15,6 +16,7 @@
 #define CQSPI_READ_CAPTURE_MAX_DELAY   16
 
 struct cadence_spi_platdata {
+       unsigned int    ref_clk_hz;
        unsigned int    max_hz;
        void            *regbase;
        void            *ahbbase;
@@ -22,6 +24,8 @@ struct cadence_spi_platdata {
        u32             fifo_depth;
        u32             fifo_width;
        u32             trigger_address;
+       fdt_addr_t      ahbsize;
+       bool            use_dac_mode;
 
        /* Flash parameters */
        u32             page_size;
@@ -43,27 +47,29 @@ struct cadence_spi_priv {
        unsigned int    qspi_calibrated_hz;
        unsigned int    qspi_calibrated_cs;
        unsigned int    previous_hz;
+
+       struct reset_ctl_bulk resets;
 };
 
 /* Functions call declaration */
 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
 void cadence_qspi_apb_controller_enable(void *reg_base_addr);
 void cadence_qspi_apb_controller_disable(void *reg_base_addr);
+void cadence_qspi_apb_dac_mode_enable(void *reg_base);
 
 int cadence_qspi_apb_command_read(void *reg_base_addr,
-       unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
+                                 const struct spi_mem_op *op);
 int cadence_qspi_apb_command_write(void *reg_base_addr,
-       unsigned int cmdlen, const u8 *cmdbuf,
-       unsigned int txlen,  const u8 *txbuf);
+                                  const struct spi_mem_op *op);
 
-int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
-       unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
-int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
-       unsigned int rxlen, u8 *rxbuf);
-int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
-       unsigned int cmdlen, const u8 *cmdbuf);
-int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
-       unsigned int txlen, const u8 *txbuf);
+int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
+                               const struct spi_mem_op *op);
+int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
+                                 const struct spi_mem_op *op);
+int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
+                                const struct spi_mem_op *op);
+int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
+                                  const struct spi_mem_op *op);
 
 void cadence_qspi_apb_chipselect(void *reg_base,
        unsigned int chip_select, unsigned int decoder_enable);