rockchip: spi: Avoid setting the pinctrl twice

[oweals/u-boot.git] / drivers / spi / Kconfig

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9c6c5d51e89e2b069127066ae9be17b06828085d..2cdb11025f88afea542ef70d552bc84709068547 100644 (file)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -15,6 +15,14 @@ config DM_SPI
 
 if DM_SPI
 
+config ALTERA_SPI
+       bool "Altera SPI driver"
+       help
+         Enable the Altera SPI driver. This driver can be used to
+         access the SPI NOR flash on platforms embedding this Altera
+         IP core. Please find details on the "Embedded Peripherals IP
+         User Guide" of Altera.
+
 config CADENCE_QSPI
        bool "Cadence QSPI driver"
        help
@@ -29,6 +37,13 @@ config DESIGNWARE_SPI
          access the SPI NOR flash on platforms embedding this Designware
          IP core.
 
+config EXYNOS_SPI
+       bool "Samsung Exynos SPI driver"
+       help
+         Enable the Samsung Exynos SPI driver. This driver can be used to
+         access the SPI NOR flash on platforms embedding this Samsung
+         Exynos IP core.
+
 config FSL_DSPI
        bool "Freescale DSPI driver"
        help
@@ -37,6 +52,28 @@ config FSL_DSPI
          this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
          use this driver.
 
+config FSL_QSPI
+       bool "Freescale QSPI driver"
+       help
+         Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
+         used to access the SPI NOR flash on platforms embedding this
+         Freescale IP core.
+
+config ICH_SPI
+       bool "Intel ICH SPI driver"
+       help
+         Enable the Intel ICH SPI driver. This driver can be used to
+         access the SPI NOR flash on platforms embedding this Intel
+         ICH IP core.
+
+config ROCKCHIP_SPI
+       bool "Rockchip SPI driver"
+       help
+         Enable the Rockchip SPI driver, used to access SPI NOR flash and
+         other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
+         This uses driver model and requires a device tree binding to
+         operate.
+
 config SANDBOX_SPI
        bool "Sandbox SPI driver"
        depends on SANDBOX && DM
@@ -62,6 +99,37 @@ config SANDBOX_SPI
                };
          };
 
+config TEGRA114_SPI
+       bool "nVidia Tegra114 SPI driver"
+       help
+         Enable the nVidia Tegra114 SPI driver. This driver can be used to
+         access the SPI NOR flash on platforms embedding this nVidia Tegra114
+         IP core.
+
+         This controller is different than the older SoCs SPI controller and
+         also register interface get changed with this controller.
+
+config TEGRA20_SFLASH
+       bool "nVidia Tegra20 Serial Flash controller driver"
+       help
+         Enable the nVidia Tegra20 Serial Flash controller driver. This driver
+         can be used to access the SPI NOR flash on platforms embedding this
+         nVidia Tegra20 IP core.
+
+config TEGRA20_SLINK
+       bool "nVidia Tegra20/Tegra30 SLINK driver"
+       help
+         Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
+         be used to access the SPI NOR flash on platforms embedding this
+         nVidia Tegra20/Tegra30 IP cores.
+
+config TEGRA210_QSPI
+       bool "nVidia Tegra210 QSPI driver"
+       help
+         Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
+         be used to access SPI chips on platforms embedding this
+         NVIDIA Tegra210 IP core.
+
 config XILINX_SPI
        bool "Xilinx SPI driver"
        help
@@ -72,14 +140,30 @@ config XILINX_SPI
 
 config ZYNQ_SPI
        bool "Zynq SPI driver"
-       depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
+       depends on ARCH_ZYNQ || ARCH_ZYNQMP
        help
          Enable the Zynq SPI driver. This driver can be used to
          access the SPI NOR flash on platforms embedding this Zynq
          SPI IP core.
 
+config ZYNQ_QSPI
+       bool "Zynq QSPI driver"
+       depends on ARCH_ZYNQ
+       help
+         Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
+         used to access the SPI NOR flash on platforms embedding this
+         Zynq QSPI IP core. This IP is used to connect the flash in
+         4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+
 endif # if DM_SPI
 
+config FSL_ESPI
+       bool "Freescale eSPI driver"
+       help
+         Enable the Freescale eSPI driver. This driver can be used to
+         access the SPI interface and SPI NOR flash on platforms embedding
+         this Freescale eSPI IP core.
+
 config TI_QSPI
        bool "TI QSPI driver"
        help