usb: ehci-mx6: Fix bus enumeration for iMX7 SoCs

[oweals/u-boot.git] / drivers / serial / serial_stm32.h

diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h
index d08ba1f55fc4021074febc052621063e3363cd3d..7b0c53145e8b722cec880625f9a99d652a2dc0a8 100644 (file)
--- a/drivers/serial/serial_stm32.h
+++ b/drivers/serial/serial_stm32.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _SERIAL_STM32_
@@ -12,6 +11,9 @@
 #define CR3_OFFSET(x)  (x ? 0x14 : 0x08)
 #define BRR_OFFSET(x)  (x ? 0x08 : 0x0c)
 #define ISR_OFFSET(x)  (x ? 0x00 : 0x1c)
+
+#define ICR_OFFSET     0x20
+
 /*
  * STM32F4 has one Data Register (DR) for received or transmitted
  * data, so map Receive Data Register (RDR) and Transmit Data
@@ -23,28 +25,24 @@
 struct stm32_uart_info {
        u8 uart_enable_bit;     /* UART_CR1_UE */
        bool stm32f4;           /* true for STM32F4, false otherwise */
-       bool has_overrun_disable;
        bool has_fifo;
 };
 
 struct stm32_uart_info stm32f4_info = {
        .stm32f4 = true,
        .uart_enable_bit = 13,
-       .has_overrun_disable = false,
        .has_fifo = false,
 };
 
 struct stm32_uart_info stm32f7_info = {
        .uart_enable_bit = 0,
        .stm32f4 = false,
-       .has_overrun_disable = true,
-       .has_fifo = false,
+       .has_fifo = true,
 };
 
 struct stm32_uart_info stm32h7_info = {
        .uart_enable_bit = 0,
        .stm32f4 = false,
-       .has_overrun_disable = true,
        .has_fifo = true,
 };
 
@@ -56,17 +54,28 @@ struct stm32x7_serial_platdata {
 };
 
 #define USART_CR1_FIFOEN               BIT(29)
+#define USART_CR1_M1                   BIT(28)
 #define USART_CR1_OVER8                        BIT(15)
+#define USART_CR1_M0                   BIT(12)
+#define USART_CR1_PCE                  BIT(10)
+#define USART_CR1_PS                   BIT(9)
 #define USART_CR1_TE                   BIT(3)
 #define USART_CR1_RE                   BIT(2)
 
 #define USART_CR3_OVRDIS               BIT(12)
 
-#define USART_SR_FLAG_RXNE             BIT(5)
-#define USART_SR_FLAG_TXE              BIT(7)
+#define USART_ISR_TXE                  BIT(7)
+#define USART_ISR_RXNE                 BIT(5)
+#define USART_ISR_ORE                  BIT(3)
+#define USART_ISR_FE                   BIT(1)
+#define USART_ISR_PE                   BIT(0)
 
 #define USART_BRR_F_MASK               GENMASK(7, 0)
 #define USART_BRR_M_SHIFT              4
 #define USART_BRR_M_MASK               GENMASK(15, 4)
 
+#define USART_ICR_ORECF                        BIT(3)
+#define USART_ICR_FECF                 BIT(1)
+#define USART_ICR_PCECF                        BIT(0)
+
 #endif