* Copy and modify from linux/drivers/serial/sh-sci.h
*/
+#include <dm/platform_data/serial_sh.h>
+
struct uart_port {
unsigned long iobase; /* in/out[bwl] */
unsigned char *membase; /* read/write[bwl] */
unsigned long mapbase; /* for ioremap */
- unsigned int type; /* port type */
+ enum sh_serial_type type; /* port type */
+ enum sh_clk_mode clk_mode; /* clock mode */
};
-#define PORT_SCI 52
-#define PORT_SCIF 53
-#define PORT_SCIFA 83
-#define PORT_SCIFB 93
-
-#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
-#include <asm/regs306x.h>
-#endif
-#if defined(CONFIG_H8S2678)
-#include <asm/regs267x.h>
-#endif
-
#if defined(CONFIG_CPU_SH7706) || \
defined(CONFIG_CPU_SH7707) || \
defined(CONFIG_CPU_SH7708) || \
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
#elif defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
# define PORT_PTCR 0xA405011EUL
# define PORT_PVCR 0xA4050122UL
# define SCIF_ORER 0x0200 /* overrun error bit */
-#elif defined(CONFIG_SH_RTS7751R2D)
-# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
-# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7750S) || \
- defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R)
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
-#elif defined(CONFIG_CPU_SH7760)
-# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
-# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
-# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define PACR 0xa4050100
# define PBCR 0xa4050102
# define SCSCR_INIT(port) 0x3B
-#elif defined(CONFIG_CPU_SH7343)
-# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
-# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
-# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
-# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
-# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
#elif defined(CONFIG_CPU_SH7722)
# define PADR 0xA4050120
# undef PSDR
# define PSCR 0xA405011E
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7366)
-# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
-# define SCSPTR0 SCPDR0
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7723)
# define SCSPTR0 0xa4050160
# define SCSPTR1 0xa405013e
# define SCSPTR5 0xa4050128
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7724)
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
- 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
- 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
#elif defined(CONFIG_CPU_SH7734)
# define SCSPTR0 0xFFE40020
# define SCSPTR1 0xFFE41020
# define SCSPTR5 0xFFE45020
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH4_202)
-# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
-# define SCIF_BASE_ADDR 0x01030000
-# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
-# define SCIF_PTR2_OFFS 0x0000020
-# define SCIF_LSR2_OFFS 0x0000024
-# define SCSPTR\
- ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
-# define SCLSR2\
- ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
-#elif defined(CONFIG_H8S2678)
-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
#elif defined(CONFIG_CPU_SH7757) || \
defined(CONFIG_CPU_SH7752) || \
defined(CONFIG_CPU_SH7753)
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7770)
-# define SCSPTR0 0xff923020 /* 16 bit SCIF */
-# define SCSPTR1 0xff924020 /* 16 bit SCIF */
-# define SCSPTR2 0xff925020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
#elif defined(CONFIG_CPU_SH7780)
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
-#if defined(CONFIG_SH_SH2007)
-/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
-# define SCSCR_INIT(port) 0x38
-#else
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
# define SCSCR_INIT(port) 0x3a
-#endif
-#elif defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)
-# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
-# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
-# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
-# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
-# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
-# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* Overrun error bit */
-# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7201) || \
- defined(CONFIG_CPU_SH7203) || \
- defined(CONFIG_CPU_SH7206) || \
- defined(CONFIG_CPU_SH7263) || \
+#elif defined(CONFIG_CPU_SH7203) || \
defined(CONFIG_CPU_SH7264)
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
-# if defined(CONFIG_CPU_SH7201)
-# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
-# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
-# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
-# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
-# endif
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7269)
+#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7619)
-# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
-# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
-# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SHX3)
-# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
-# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
-# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
-# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* Overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
-# define SCIF_ORER 0x0001
-# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
+ defined(CONFIG_R7S72100)
+# if defined(CONFIG_SCIF_A)
+# define SCIF_ORER 0x0200
+# else
+# define SCIF_ORER 0x0001
+# endif
+# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
+ /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
# error CPU subtype not defined
#endif
#define SCI_CTRL_FLAGS_TE 0x20 /* all */
#define SCI_CTRL_FLAGS_RE 0x10 /* all */
#if defined(CONFIG_CPU_SH7750) || \
- defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7722) || \
defined(CONFIG_CPU_SH7734) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7763) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786) || \
- defined(CONFIG_CPU_SHX3)
+ defined(CONFIG_CPU_SH7780)
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
-#elif defined(CONFIG_CPU_SH7724)
-#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
#else
#define SCI_CTRL_FLAGS_REIE 0
#endif
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCIF_ORER 0x0200
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+#elif defined(CONFIG_RCAR_GEN2)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
-# define SCIF_RFDC_MASK 0x003f
+# if defined(CONFIG_SCIF_A)
+# define SCIF_RFDC_MASK 0x007f
+# else
+# define SCIF_RFDC_MASK 0x001f
+# endif
#else
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x001f
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
}\
}
-#ifdef CONFIG_H8300
-/* h8300 don't have SCIF */
-#define CPU_SCIF_FNS(name) \
- static inline unsigned int sci_##name##_in(struct uart_port *port) {\
- return 0;\
- }\
- static inline void sci_##name##_out(struct uart_port *port,\
- unsigned int value) {\
- }
-#else
#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
SCI_IN(scif_size, scif_offset);\
unsigned int value) {\
SCI_OUT(scif_size, scif_offset, value);\
}
-#endif
#define CPU_SCI_FNS(name, sci_offset, sci_size)\
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
SCI_OUT(sci_size, sci_offset, value);\
}
-#if defined(CONFIG_SH3) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#if defined(CONFIG_CPU_SH3) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
#elif defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_SH73A0)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
-#elif defined(CONFIG_ARCH_SH7372) || \
- defined(CONFIG_R8A7740)
+#elif defined(CONFIG_R8A7740)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scifb_offset, sh4_scifb_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
#endif
-#elif defined(__H8300H__) || defined(__H8300S__)
-#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
- sh4_sci_offset, sh4_sci_size, \
- sh3_scif_offset, sh3_scif_size,\
- sh4_scif_offset, sh4_scif_size, \
- h8_sci_offset, h8_sci_size) \
- CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
-#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
- sh4_scif_offset, sh4_scif_size) \
- CPU_SCIF_FNS(name)
-#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7723)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_SH73A0)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCxTDR, 0x20, 8)
SCIF_FNS(SCxRDR, 0x24, 8)
SCIF_FNS(SCLSR, 0x00, 0)
-#elif defined(CONFIG_ARCH_SH7372) || \
- defined(CONFIG_R8A7740)
+SCIF_FNS(DL, 0x00, 0) /* dummy */
+#elif defined(CONFIG_R8A7740)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
SCIF_FNS(SCSCR, 0x08, 16)
SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
SCIF_FNS(SCLSR, 0x00, 0)
-#elif defined(CONFIG_CPU_SH7723) ||\
- defined(CONFIG_CPU_SH7724)
+SCIF_FNS(DL, 0x00, 0) /* dummy */
+#elif defined(CONFIG_CPU_SH7723)
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
SCIF_FNS(SCFCR, 0x18, 16)
SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCLSR, 0x24, 16)
+SCIF_FNS(DL, 0x00, 0) /* dummy */
+#elif defined(CONFIG_RCAR_GEN2)
+/* SCIFA and SCIF register offsets and size */
+SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
+SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
+SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
+SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
+SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
+SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
+SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
+SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
+SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
+SCIF_FNS(DL, 0, 0, 0x30, 16)
+SCIF_FNS(CKS, 0, 0, 0x34, 16)
+#if defined(CONFIG_SCIF_A)
+SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
+#else
+SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
+#endif
#else
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
/* name off sz off sz off sz off sz off sz*/
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
-#if defined(CONFIG_CPU_SH7760) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)
+#if defined(CONFIG_CPU_SH7780)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
#else
+
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
#if defined(CONFIG_CPU_SH7722)
SCIF_FNS(SCSPTR, 0, 0, 0, 0)
#else
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
#endif
-#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
-SCIF_FNS(DL, 0, 0, 0x30, 16)
-SCIF_FNS(CKS, 0, 0, 0x34, 16)
-#endif
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
+SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
#endif
#define sci_in(port, reg) sci_##reg##_in(port)
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
-/* H8/300 series SCI pins assignment */
-#if defined(__H8300H__) || defined(__H8300S__)
-static const struct __attribute__((packed)) {
- int port; /* GPIO port no */
- unsigned short rx, tx; /* GPIO bit no */
-} h8300_sci_pins[] = {
-#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
- { /* SCI0 */
- .port = H8300_GPIO_P9,
- .rx = H8300_GPIO_B2,
- .tx = H8300_GPIO_B0,
- },
- { /* SCI1 */
- .port = H8300_GPIO_P9,
- .rx = H8300_GPIO_B3,
- .tx = H8300_GPIO_B1,
- },
- { /* SCI2 */
- .port = H8300_GPIO_PB,
- .rx = H8300_GPIO_B7,
- .tx = H8300_GPIO_B6,
- }
-#elif defined(CONFIG_H8S2678)
- { /* SCI0 */
- .port = H8300_GPIO_P3,
- .rx = H8300_GPIO_B2,
- .tx = H8300_GPIO_B0,
- },
- { /* SCI1 */
- .port = H8300_GPIO_P3,
- .rx = H8300_GPIO_B3,
- .tx = H8300_GPIO_B1,
- },
- { /* SCI2 */
- .port = H8300_GPIO_P5,
- .rx = H8300_GPIO_B1,
- .tx = H8300_GPIO_B0,
- }
-#endif
-};
-#endif
-
#if defined(CONFIG_CPU_SH7706) || \
defined(CONFIG_CPU_SH7707) || \
defined(CONFIG_CPU_SH7708) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7750R) || \
- defined(CONFIG_CPU_SH7750S) || \
- defined(CONFIG_CPU_SH7091)
+ defined(CONFIG_CPU_SH7750S)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
return 1;
}
-#elif defined(__H8300H__) || defined(__H8300S__)
-static inline int sci_rxd_in(struct uart_port *port)
-{
- int ch = (port->mapbase - SMR0) >> 3;
- return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
-}
#else /* default case for non-SCI processors */
static inline int sci_rxd_in(struct uart_port *port)
{
* -- Mitch Davis - 15 Jul 2000
*/
-#if (defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)) && \
- !defined(CONFIG_SH_SH2007)
+#if defined(CONFIG_CPU_SH7780)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
-#elif defined(CONFIG_CPU_SH7723) ||\
- defined(CONFIG_CPU_SH7724)
-static inline int scbrr_calc(struct uart_port port, int bps, int clk)
+#elif defined(CONFIG_CPU_SH7723)
+static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
{
- if (port.type == PORT_SCIF)
+ if (port->type == PORT_SCIF)
return (clk+16*bps)/(32*bps)-1;
else
return ((clk*2)+16*bps)/(16*bps)-1;
}
-#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
-#elif defined(__H8300H__) || defined(__H8300S__)
-#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
+#elif defined(CONFIG_RCAR_GEN2)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */
+ #if defined(CONFIG_SCIF_A)
+ #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
+ #else
+ #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
+ #endif
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
+
+#ifndef DL_VALUE
+#define DL_VALUE(bps, clk) 0
+#endif
projects / oweals / u-boot.git / blobdiff