#include <common.h>
#include <errno.h>
+#include <clk.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/processor.h>
#ifdef CONFIG_OF_CONTROL
static const struct udevice_id sh_serial_id[] ={
+ {.compatible = "renesas,sci", .data = PORT_SCI},
{.compatible = "renesas,scif", .data = PORT_SCIF},
{.compatible = "renesas,scifa", .data = PORT_SCIFA},
{}
static int sh_serial_ofdata_to_platdata(struct udevice *dev)
{
struct sh_serial_platdata *plat = dev_get_platdata(dev);
+ struct clk sh_serial_clk;
fdt_addr_t addr;
+ int ret;
- addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = addr;
- plat->clk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+
+ ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
+ if (!ret) {
+ ret = clk_enable(&sh_serial_clk);
+ if (!ret)
+ plat->clk = clk_get_rate(&sh_serial_clk);
+ } else {
+ plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "clock", 1);
+ }
+
plat->type = dev_get_driver_data(dev);
return 0;
}
#if defined(CONFIG_SCIF_A)
#define SCIF_BASE_PORT PORT_SCIFA
+#elif defined(CONFIG_SCI)
+ #define SCIF_BASE_PORT PORT_SCI
#else
#define SCIF_BASE_PORT PORT_SCIF
#endif