Merge branch 'master' of /home/stefan/git/u-boot/u-boot

[oweals/u-boot.git] / drivers / serial / serial_sh.c

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index ee44ba26445c356d91a078364b89dce487b561dd..aa4ff35333ac1c5a363eb739877dec419a9a5cfe 100644 (file)
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -1,6 +1,6 @@
 /*
  * SuperH SCIF device driver.
- * Copyright (c) 2007 Nobuhiro Iwamatsu
+ * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -30,47 +30,73 @@
 #error "Default SCIF doesn't set....."
 #endif
 
-#define SCSMR  (vu_short *)(SCIF_BASE + 0x0)
-#define SCBRR  (vu_char  *)(SCIF_BASE + 0x4)
-#define SCSCR  (vu_short *)(SCIF_BASE + 0x8)
-#define SCFTDR         (vu_char  *)(SCIF_BASE + 0xC)
-#define SCFSR  (vu_short *)(SCIF_BASE + 0x10)
-#define SCFRDR         (vu_char  *)(SCIF_BASE + 0x14)
-#define SCFCR  (vu_short *)(SCIF_BASE + 0x18)
-#define SCFDR  (vu_short *)(SCIF_BASE + 0x1C)
-#if defined(CONFIG_SH4A)
-#define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
-#define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
-#define SCLSR   (vu_short *)(SCIF_BASE + 0x28)
-#define SCRER  (vu_short *)(SCIF_BASE + 0x2C)
-#elif defined (CONFIG_SH4)
-#define SCSPTR         (vu_short *)(SCIF_BASE + 0x20)
-#define SCLSR  (vu_short *)(SCIF_BASE + 0x24)
-#elif defined (CONFIG_SH3)
-#define SCLSR  (vu_short *)(SCIF_BASE + 0x24)
+/* Base register */
+#define SCSMR  (vu_short *)(SCIF_BASE + 0x0)
+#define SCBRR  (vu_char  *)(SCIF_BASE + 0x4)
+#define SCSCR  (vu_short *)(SCIF_BASE + 0x8)
+#define SCFCR  (vu_short *)(SCIF_BASE + 0x18)
+#define SCFDR  (vu_short *)(SCIF_BASE + 0x1C)
+#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
+# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
+# define SCFTDR        (vu_char  *)(SCIF_BASE + 0x20)
+# define SCFRDR        (vu_char  *)(SCIF_BASE + 0x24)
+#else
+# define SCFTDR (vu_char  *)(SCIF_BASE + 0xC)
+# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
+# define SCFRDR (vu_char  *)(SCIF_BASE + 0x14)
+#endif
+
+#if defined(CONFIG_CPU_SH7780) || \
+       defined(CONFIG_CPU_SH7785)
+# define SCRFDR        (vu_short *)(SCIF_BASE + 0x20)
+# define SCSPTR        (vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
+# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
+# define LSR_ORER      1
+# define FIFOLEVEL_MASK        0xFF
+#elif defined(CONFIG_CPU_SH7750) || \
+       defined(CONFIG_CPU_SH7751) || \
+       defined(CONFIG_CPU_SH7722)
+# define SCSPTR        (vu_short *)(SCIF_BASE + 0x20)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER      1
+# define FIFOLEVEL_MASK        0x1F
+#elif defined(CONFIG_CPU_SH7720)
+# define SCLSR  (vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER      0x0200
+# define FIFOLEVEL_MASK        0x1F
+#elif defined(CONFIG_CPU_SH7710)
+       defined(CONFIG_CPU_SH7712)
+# define SCLSR SCFSR   /* SCSSR */
+# define LSR_ORER      1
+# define FIFOLEVEL_MASK        0x1F
 #endif
 
-#define SCR_RE                 (1 << 4)
-#define SCR_TE                 (1 << 5)
+/* SCBRR register value setting */
+#if defined(CONFIG_CPU_SH7720)
+# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+#else  /* Generic SuperH */
+# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
+#endif
+
+#define SCR_RE         (1 << 4)
+#define SCR_TE         (1 << 5)
 #define FCR_RFRST      (1 << 1) /* RFCL */
 #define FCR_TFRST      (1 << 2) /* TFCL */
-#define FSR_DR         (1 << 0)
-#define FSR_RDF        (1 << 1)
-#define FSR_FER        (1 << 3)
-#define FSR_BRK        (1 << 4)
-#define FSR_FER        (1 << 3)
-#define FSR_TEND       (1 << 6)
-#define FSR_ER         (1 << 7)
+#define FSR_DR         (1 << 0)
+#define FSR_RDF                (1 << 1)
+#define FSR_FER                (1 << 3)
+#define FSR_BRK                (1 << 4)
+#define FSR_FER                (1 << 3)
+#define FSR_TEND       (1 << 6)
+#define FSR_ER         (1 << 7)
 
 /*----------------------------------------------------------------------*/
 
 void serial_setbrg (void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       int divisor = gd->baudrate * 32;
-
-       *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) /
-                                               (gd->baudrate * 32) - 1;
+       *SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ);
 }
 
 int serial_init (void)
@@ -86,14 +112,13 @@ int serial_init (void)
        return 0;
 }
 
-static int serial_tx_fifo_level (void)
-{
-       return (*SCFDR >> 8) & 0x1F;
-}
-
 static int serial_rx_fifo_level (void)
 {
-       return (*SCFDR >> 0) & 0x1F;
+#if defined(CONFIG_SH4A)
+       return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
+#else
+       return (*SCFDR >> 0) & FIFOLEVEL_MASK;
+#endif
 }
 
 void serial_raw_putc (const char c)
@@ -131,9 +156,8 @@ int serial_tstc (void)
        return serial_rx_fifo_level() ? 1 : 0;
 }
 
-#define FSR_ERR_CLEAR   0x0063
-#define RDRF_CLEAR      0x00fc
-#define LSR_ORER        1
+#define FSR_ERR_CLEAR  0x0063
+#define RDRF_CLEAR     0x00fc
 void handle_error( void ){
 
        (void)*SCFSR ;